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path: root/src/soc/intel/cannonlake/acpi/southbridge.asl
AgeCommit message (Expand)Author
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-03-04soc/intel/cnl/acpi: add ish ACPI deviceJett Rink
2018-11-15soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devicesSubrata Banik
2018-11-07mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT gener...Subrata Banik
2018-10-17soc/intel/cannonlake: Add CNP PCH-H gpio pin definitionspraveen hodagatta pranesh
2018-10-09soc/intel/cannonlake: Add PCIE ASL entrySubrata Banik
2018-10-09soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devicesSubrata Banik
2018-09-28soc/intel/cannonlake: Add ACPI entry for LANLijian Zhao
2018-08-30soc/intel/cannonlake: Fix comment errors for SMBUSLijian Zhao
2018-02-22soc/intel/cannonlake: Clear EMMC timeout registerLijian Zhao
2018-02-16soc/intel/cannonlake: Use common PCR ASLLijian Zhao
2017-12-13src/soc/intel/cannonlake: Add _PRW for CNViBora Guvendik
2017-10-05soc/intel/cannonlake: Add all the SOC level DSDT tablesLijian Zhao
2017-10-03soc/intel/cannonlake: add initial ASL methods for SCS, GPIOBora Guvendik
2017-09-19soc/intel/cannonlake: Add PCIE IRQsBora Guvendik