Age | Commit message (Collapse) | Author |
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This replaces GPLv2-or-later and GPLv2-only long form text with the
short SPDX identifiers.
Commands used:
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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That makes it easier to identify "license only" headers (because they
are now license only)
Script line used for that:
perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist...
Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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According to doc 621880, it suggests setting 40 ohm in byte 185 in extCSD.
This commit provides _DSM method for driver to query driving strength.
TEST=mmc extcsd read |grep HS_TIMING and found bit[7:4] is set to 4
BUG=b:154159888
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I1b4df8b0d1d2cad3a7f521ad47ee5a4b3320c767
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: Ib156ebede1ee24a1c7bd20d01792ec80cba8f37d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I48422453735d50eb9292f39a3c031073d647a17c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This patch fixes below ASL compilation remarks
1. dsdt.asl 495: Method (_DSM, 4)
Remark 2119 - ^ Control Method marked Serialized (Due to use of Switch operator)
2.
dsdt.asl 721: Name(GPMB, Package(5) {0})
Remark 2063 - ^ Initializer list shorter than declared package length
Change-Id: Iabd6c39025713dda7aa69cb479f003fbec8855b3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch creates a common instance of northbridge.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to
refer northbridge.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
Device(MCHC) presence after booting to OS.
Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes in this patch
1. Remove unused variables
2. Make use of absolute path
3. Define macros and use inside SA ASL
4. Rearrange code in nothbridge.asl to move MCRS object under _CRS
Change-Id: Id74269ec5a96b087562ccdf2141233db5585ae59
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
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Enable GPIO clock gating when enter s0ix/Sx and save the PM bits.
Restore the PM bits when exit s0ix/Sx.
BUG=b:144002424
TEST=Check GPIO PM bits when enter/exit s0ix are expected
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The base address of the 16 MB flash range was reported as 0xFFF00000
this causes the range to extend above the 4GB boundary.
Change the base to 0xFF000000 as is the case with e.g. Skylake.
BUG=N/A
TEST=build
Change-Id: Ia8de01769ced00c5ae13f255760401933230b88c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Add gfx.asl file for cannonlake SOCs to allow for graphics-related ACPI
devices and methods on cannonlake devices.
BUG=b:142237145
TEST=gfx.asl added to drallion dsdt.asl
Change-Id: I38a26f3135d571e2f9b63840d38fd4d3476fc142
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This patch creates a common instance of ipu.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and ask cnl & icl soc code to
refer ipu.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
Device(IMGU) presence after booting to OS.
Change-Id: I4d18571008c199fd5c3dbeed8cba9374520359b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch creates a common instance of globalnvs.asl/nvs.h inside intel common
code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl
and nvs.h from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
GNVS operation region presence after booting to OS.
Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch creates a common instance of sleepstates.asl inside intel common
code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to
refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch creates a common instance of lpc.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and asks specific soc code to
refer lpc.asl from common code block.
Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI
rather than LPC.
TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify
Device(LPCB) device presence after booting to OS.
Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36455
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=Able to build and boot Hatch and DE.
Change-Id: I6d63c005873fc5d67b4a44f42bb436628d7c1dc3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36462
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Change-Id: I09fce1298794f30c1db699438204ac32ee9cb27d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36296
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1f970db22f87e8eba0129ca049f75d16539644a5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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The GPID method returns the PCR Port ID of the given GPIO community.
The CGPM method alters the given GPIO community's PM bits, given in
Arg1.
Change-Id: I098ee08573eb4f8a45d9b5ae84f2d85ce525c9b8
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Only call the \_SB.PCI0.LPCB.EC0.S0IX method if it exists.
Change-Id: Idf465f8ad7cb016f3ad3d9710b46e35f66f8939b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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The SD controller seems to take some time after restarting
the clock at 1.8V before it actually switches from 3.3V to
1.8V. Add a _DSM method that simply sleeps when switching
between 3.3V and 1.8V. Otherwise, the kernel times out too
quickly waiting for the card to acknowledge the 1.8V switch.
The card itself is waiting until it sees the clk signal being
driven at 1.8V.
BUG=b:125441242
TEST=Boot Hatch with SD card and CR2 removed, observe voltage
switch succeeds.
Change-Id: I15090ed9f9bc90b35dfcba47c913e3d37b799d0b
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signef-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add board level s0ix call back. Since some driver doesn't
care _ON/_OFF method. Add a control method for s0ix usage.
BUG=b:129177593
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I404f388b19355ae89b36d1fb07f9fb4f97eb3b2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Create the ISH ACPI device so we can hang fields off of a _DSD table.
Since this is also a PCI device that has run time probing, we can always
emit the ACPI device and let the device tree turn the device on or off.
BRANCH=none
BUG=b:122722008
TEST=verify that _DSD table gets publish under ISH device in kernel ACPI
tables. Also verified that device is still turned off if device tree for
ISH is off.
Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The following remarks show up during cannonlake based platform coreboot
build:
dsdt.asl 55: Offset (0x00),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 136: Offset (0xa8),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Address those two remarks in coreboot.
BUG=N/A
TEST=Build coreboot and check build log to see no more remark.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe
Reviewed-on: https://review.coreboot.org/c/31666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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SD controller in CNL-PCH provides a ability to configure the behavior of
SD_VDD1_PWR_EN# as an active high or low signal. FSP provides an UPD
"SdCardPowerEnableActiveHigh" to control the same.
However, for platforms using SD_VDD1_PWR_EN# as active high, the SDXC
card connector is always powered and may impact system power. This is because
SD_VDD1_PWR_EN# does not de-assert during SDXC D3 or when SD card is not
inserted.
Workaround is to change the pad ownership of SD_VDD1_PWR_EN to GPIO and
force the TX buffer to low in _PS3. And restore the pad mode to native
function in _PS0.
Hence add a Kconfig option to update the UPD, which the board can select
based on how the SD_VDD1_PWR_EN is implemented on it. And, the workaround
gets applied based on this config.
BUG=b:123350329
Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31445
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a function in gpio ASL library to enable/disable pad Rx/Tx Buffers.
BUG=b:123350329
Change-Id: I6c40d79debb61b0c4e96e485b410d446b77d9cf6
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Denote appropriate reserved groups as virtual GPIOs in Cannonlake LP/H SoC.
Change-Id: I4da161b91f83749b0ae29b387b5c99c1c3f706d8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add a function in gpio ASL library to set pad mode.
BUG=b:123350329
Change-Id: I6c683f27ddffc3132001706d1694c71bb5664577
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch adds the _DSM method 5 and 6 for entering and exiting S0ix.
The _DSM method gets injected into DSDT table and called from kernel.
LPIT table is hardcoded in this patch but the proper way to implement
is to use inject_dsdt to make the _DSM methods available for soc's to
implement.
Calling the LPIT table from mainboard here so that with the current
implementation the platforms which do not have lpit support throw
compilation error.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db
Reviewed-on: https://review.coreboot.org/c/31101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Replace device name from B0D4 with TCPU for DPTF sensor. This
helps to maintain consistency between coreboot and UEFI BIOS.
Change-Id: I962d74fc1baa07581d065734aaabb4dcd5e3d247
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Follow instrcution from https://doc.coreboot.org/acpi/gpio.html to
implement GPIO toggling method, covered for both CNP_LP and CNP_H pch.
BUG=N/A
TEST=Build and boot up fine on sarien platform, add an dummy STSX in
DSDT table, read back from iotools to confirm the GPIO tx state get
updated.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f
Reviewed-on: https://review.coreboot.org/c/30461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The kernel GPIO driver only expects some GPIO communities to be exported
in the _CRS and it will not work correctly if the other communities are
exported.
CNL-LP: GPIO communities 0, 1, 4
CNL-H: GPIO communities 0, 1, 3, 4
Additionally one of the pin offset values was incorrect in GPIO
community 1 for CNL-LP. This doesn't have any specific failure mode but
it was found when auditing the GPIO code.
Details of the kernel expected map can be found in the linux kernel at
drivers/pinctrl/intel/pinctrl-cannonlake.c
BUG=b:120686247
TEST=check /sys/kernel/debug/pinctrl/INT34BB:00/pins to ensure that
pins >= 198 are not reading all zeros for the pin config registers.
Change-Id: Ie1a2f3b9f9f4b24a9fc57e468dee50e99753912f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Define the constants that DPTF expects from the SOC in order to
use the common DPTF ACPI code. For cannonlake this indicates
the CPU device is called B0D4 and is at PCI address 00:04.0.
Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29759
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
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Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call
due to PCH requirement change from CNP PCH onwards, hence making static IRQ
mapping for pci_irqs.asl and pcie.asl
Also remove unused irqlinks.asl from soc/intel/cannonlake/acpi/
Change-Id: I35e2ed150a1db195fc9ce13897e65b23fc8b7ca1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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generation
This changes uses drivers/intel/wifi chip for CNVi device to ensure that:
1. Correct device name shows in ACPI name space
2. Correct wake up shows in cat /proc/acpi/wakeup
3. Remove cnvi.asl from soc/intel/cannonlake
Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add ACPI entry in sleepstates.asl to support S4 (hibernate).
TEST: boot to Windows on CFL RVP11 & RVP8, verified hibernate functionality.
Change-Id: I751c774e6ec7fd89ac3af5a619033bd38a759281
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities.
- Add gpio pin definitions for CNP-H and related changes.
- Add gpio device name, host software ownership reg offset for CNP-H.
BUG: none
TEST: build and flash, boot to windows and yocto os on both CFL RVP8 &
RVP11 and verify power management, IO device functionalities
work fine.
Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch creates _PRT entires for each PCIE root port devices.
TEST=Able to see PCIE wake device in cat /proc/acpi/wake list
Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch provides option for PCI IRQ mapping in both PIC and APIC mode.
TEST=Build and Boot on CNL RVP.
Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add ACPI DSDT entry for integrated Gigabit LAN controller.
Change-Id: I15bf1d4065894531871380b3318f553b637f4a97
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28743
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On CannonLake PCH, SMBUS stays at Bus 0 Device 31 and Function 4,
previous comment in southbridge.asl mention it as Function 3 that was a
mistake.
BUG=N/A
TEST=N/A
Change-Id: I29786457379809b6fcb592e1136ff612539e24dc
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide. _PS0 is not called by kernel when boot source is not
EMMC but kernel still initializes emmc. Add _INI to EMMC,SD asl code to
cover cases that the system doesn't boot from EMMC.
BUG=b:76202699
TEST=Install OS into EMMC
Change-Id: I4eef23f637f781b709696951c5bd825530cc1d11
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/25290
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide.
BUG=b.71586766
TEST=Install OS into EMMC successfully on meowth P1 platform.
Change-Id: I39e927a2c312c94561213f9f7c3319dcafa426b9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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GPIO pin definition had been updated to match Cannonlake PCH-LP EDS,
hence the ACPI dsdt table will include those changes as well.
BUG=None
TEST=Build coreboot image, flah coreboot image into DUT, and target
system can boot up into OS.
Change-Id: I958e0cb71b4e656bec9bfe2d12076b577b57629b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Switch to use common version of PCR asl.
BUG=NONE
TEST=Boot up into chrome OS properly on cannonlake rvp platform.
Change-Id: I4975704434d4743bcc0fb6062115da349166c3a6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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For the internal eMMC to be used by non-chrome for installation,
the CARD device and _RMV methods are required. Without these,
other OSes does not show the eMMC as a valid installation target.
TEST= boot CNL-RVP with Tiano payload and install Windows 10
to the internal eMMC drive.
Change-Id: Icfdccd88bc113d97c2fabf4c63d8d772737a6057
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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