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path: root/src/soc/intel/cannonlake/acpi
AgeCommit message (Expand)Author
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-03-04soc/intel/cnl/acpi: add ish ACPI deviceJett Rink
2019-03-04soc/intel/cannonlake: Fix DSDT compile remarksLijian Zhao
2019-02-27soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#Rizwan Qureshi
2019-02-27soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffersRizwan Qureshi
2019-02-26soc/intel/cannonlake: Update GPIO definitions for Virtual GPIORizwan Qureshi
2019-02-22soc/intel/cannonlake: Add ASL function for setting pad modeRizwan Qureshi
2019-02-20src/soc/intel/cannonlake: Add _DSM methods for LPIT tableLijian Zhao
2019-01-23soc/intel/cannonlake: Replace device name B0D4 with TCPUSumeet Pawnikar
2019-01-03soc/intel/cannonlake: Add cannonlake ACPI GPIO opLijian Zhao
2018-12-10soc/intel/cannonlake: Fix GPIO reportingDuncan Laurie
2018-12-04soc/intel/cannonlake: Add DPTF ACPI codeDuncan Laurie
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
2018-11-30soc/intel/common: Rework acpi/cpu.aslArthur Heymans
2018-11-15soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devicesSubrata Banik
2018-11-07mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT gener...Subrata Banik
2018-10-25soc/intel/cannonlake: Enable S4 sleep state supportpraveen hodagatta pranesh
2018-10-17soc/intel/cannonlake: Add CNP PCH-H gpio pin definitionspraveen hodagatta pranesh
2018-10-09soc/intel/cannonlake: Add PCIE ASL entrySubrata Banik
2018-10-09soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devicesSubrata Banik
2018-09-28soc/intel/cannonlake: Add ACPI entry for LANLijian Zhao
2018-08-30soc/intel/cannonlake: Fix comment errors for SMBUSLijian Zhao
2018-04-05soc/intel/cannonlake: Clear EMMC timeout when boot source is not EMMCBora Guvendik
2018-02-22soc/intel/cannonlake: Clear EMMC timeout registerLijian Zhao
2018-02-16soc/intel/cannonlake: Update GPIO ASLLijian Zhao
2018-02-16soc/intel/cannonlake: Use common PCR ASLLijian Zhao
2018-01-24soc/intel/cannonlake: Add child CARD device into eMMC/SD controllerSubrata Banik
2018-01-24soc/intel/cannonlake: Port SD Controller W/A from Intel Reference codeSubrata Banik
2018-01-24soc/intel/cannonlake: Port eMMC controller W/A from Intel Reference codeSubrata Banik
2017-12-13src/soc/intel/cannonlake: Add _PRW for CNViBora Guvendik
2017-11-23soc/intel/cannonlake: Add PM methods to power gate SD card controllerVaibhav Shankar
2017-11-20soc/intel/cannonlake: Add ACPI workaround for EMMCLijian Zhao
2017-11-17soc/intel/cannonlake: Add cpu.asl fileShaunak Saha
2017-11-15soc/intel/cannonlake: Fix and clean up xhci ACPI codeVaibhav Shankar
2017-10-20soc/intel/cannonlake: Add platform.aslLijian Zhao
2017-10-12soc/intel/cannonlake: add length information for communitiesBora Guvendik
2017-10-12soc/intel/cannonlake: Add ACPI platform sleep capabilityVaibhav Shankar
2017-10-05soc/intel/cannonlake: Add all the SOC level DSDT tablesLijian Zhao
2017-10-03soc/intel/cannonlake: add initial ASL methods for SCS, GPIOBora Guvendik
2017-10-03soc/intel/cannonlake: Add northbridge dsdt tableLijian Zhao
2017-09-19soc/intel/cannonlake: Add PCIE IRQsBora Guvendik
2017-09-13soc/intel/cannonlake: Add common ACPI support for CNLLijian Zhao