coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-08-28	soc/intel/cnl: Add CML IGD IDs	Meera Ravindranath
2019-08-26	lib/bootblock: Add simplified entry with basetime	Kyösti Mälkki
2019-08-16	soc/intel/cannonlake: Add 4E/4F to early io init	Christian Walter
2019-08-16	soc/intel/cannonlake: Add more PCI Ids for Coffeelake	Christian Walter
2019-08-01	soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registers	David Wu
2019-07-30	soc/intel/cannonlake: Add new PCI IDs	Felix Singer
2019-07-17	soc/intel/cannonlake: Add device Ids for new CFL SKUs support	Lean Sheng Tan
2019-07-12	soc/intel/common: Add Coffee Lake H 6+2 Xeon graphics id	Nico Huber
2019-07-12	soc/intel/common: Add CM246 LPC device id	Nico Huber
2019-05-22	post_code: add post code for hardware initialization failure	Keith Short
2019-04-19	soc/intel/cannonlake: Add report for iGD 0x3ea1	Lijian Zhao
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-04	device/mmio.h: Add include file for MMIO ops	Kyösti Mälkki
2019-03-04	arch/io.h: Drop unnecessary include	Kyösti Mälkki
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2019-02-28	soc/intel/cannonlake: Add Comet Lake U SA 2+2 Device ID	Subrata Banik
2019-02-26	soc/intel/common: Include cometlake PCH IDs	Ronak Kanabar
2019-02-24	soc/intel/common: Include cometlake SA IDs	Ronak Kanabar
2019-02-24	soc/intel/common: Include cometlake CPU IDs	Ronak Kanabar
2019-02-23	soc/intel/cannonlake: Make few more whitespace proper in MCH name	Subrata Banik
2019-02-22	soc/intel/cannonlake: Add whitespace proper in CPU/MCH/IGD name	Subrata Banik
2019-02-19	soc/intel/common: Add whiskeylake celeron v-0 support	Lijian Zhao
2019-01-10	soc/intel/common/block: Move tco common functions into block/smbus	Subrata Banik
2019-01-09	soc/intel: Clean mess around UART_DEBUG	Nico Huber
2018-12-19	soc: Remove useless include <device/pci_ids.h>	Elyes HAOUAS
2018-12-13	cpuid: Add helper function for cpuid(1) functions	Subrata Banik
2018-12-03	soc/intel/cannonlake: Load FSP teardown optionally	Lijian Zhao
2018-11-21	soc/intel/cannonlake: Fix IO decode setup	Duncan Laurie
2018-10-25	soc/intel: Consolidate FSP CAR setup and teardown code	Praveen hodagatta pranesh
2018-10-17	soc/intel/cannonlake: Add new cannon lake PCH-H support	praveen hodagatta pranesh
2018-08-30	soc/intel/cannonlake: Update PMC base address for CNP H and LP	Maulik V Vaghela
2018-08-20	soc/intel/common/block: Move common uart function to block/uart	Subrata Banik
2018-08-20	soc/intel/common/block: Add WHL 2-core SKU	Krzysztof Sywula
2018-08-10	src/soc/intel: Add new device IDs to support coffeelake	Maulik
2018-08-03	soc/intel/cannonlake: Report Whiskey Lake info	Lijian Zhao
2018-07-09	src/soc: Use "foo bar" instead of "foo bar"	Elyes HAOUAS
2018-06-28	soc/intel/common/block: Move p2sb common functions into block/p2sb	Subrata Banik
2018-06-14	src: Use of device_t is deprecated	Elyes HAOUAS
2018-05-22	bootblock: Allow more timestamps in bootblock_main_with_timestamp()	Julius Werner
2018-01-26	soc/intel/cannonlake: Add Cannonlake D0 support in mpinit and report	Lijian Zhao
2018-01-25	soc/intel/cannonlake: enable pch link in bootblock	Caveh Jalali
2018-01-16	soc/intel/cannonlake: Program DMI PCR settings	Lijian Zhao
2018-01-10	soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock	Furquan Shaikh
2018-01-09	soc/intel/cannonlake: Remove redundent CNL CPUID macros	Subrata Banik
2018-01-05	soc/intel/cannonlake: Correct PMC/GPIO routing information	Lijian Zhao
2017-12-08	soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.c	Subrata Banik
2017-10-19	soc/intel/cannonlake: Fix HECI error on reset	Lijian Zhao
2017-10-18	soc/intel/cannonlake: Use EBDA area to store cbmem_top address	Subrata Banik
2017-08-21	soc/intel/cannonlake: Enable common PMC code for CNL	Lijian Zhao
2017-08-07	soc/intel/cannonlake: Add memory map support	Lijian Zhao