coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-09-04	soc/intel/cnl: Enable HECI3 depending on devicetree	Felix Singer
2020-08-23	soc/intel/cnl: Configure FSP option PcieRpSlotImplemented	Nico Huber
2020-07-01	soc/intel/cannonlake: make satahotplug user configurable via devicetree	Jonas Loeffelholz
2020-06-25	soc/intel/cannonlake: Add PchPmPwrCycDur to chip options	Sridhar Siricilla
2020-06-17	soc/intel/cannonlake: Use table instead of switch-case	Patrick Rudolph
2020-06-02	soc/intel/cannonlake: Add RP configuration settings	Christian Walter
2020-05-26	cannonlake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-26	soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip options	Christian Walter
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-04	soc/intel/cannonlake: Add DisableHeciRetry to config	Christian Walter
2020-05-01	src: Remove not used 'include <smbios.h>'	Elyes HAOUAS
2020-04-06	soc/intel/cannonlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-17	soc/intel/cannonlake: Set correct serirq mode	Jeremy Soller
2020-03-04	src: capitalize 'PCIe'	Elyes HAOUAS
2020-02-28	soc/intel/cannonlake: Plumb TetonGlacierMode into dt	Edward O'Callaghan
2020-02-04	soc/intel/cannonlake: Allow Audio DSP OSC qualification for low power idle	Aamir Bohra
2020-01-18	soc/intel/cannonlake: Add chip config for SATA strength	Jamie Chen
2020-01-08	soc/intel/cannonlake: Add VR config for CML	Jamie Chen
2019-12-12	soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h	Furquan Shaikh
2019-11-27	soc/intel/cannonlake: Disable USB2 PHY Power gating	Surendranath Gurivireddy
2019-11-26	soc/intel/cannonlake: Add chip config to override CPU flex ratio	Subrata Banik
2019-11-04	soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig	Michael Niewöhner
2019-09-29	soc/intel: Rename <intelblocks/chip.h>	Kyösti Mälkki
2019-09-12	soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usage	Subrata Banik
2019-09-12	soc/intel/cannonlake: Add config for sata devslp pad reset configuration	Aamir Bohra
2019-08-26	soc/intel/cannonlake: Add config to disable display audio codec	Aamir Bohra
2019-08-20	soc/intel/cnl: Add provision to configure SD controller write protect pin	Aamir Bohra
2019-06-28	soc/intel/cannonlake: fix use of legacy 8254 timer	Matt DeVillier
2019-06-21	soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE	Arthur Heymans
2019-05-20	soc/intel/cannonlake: Make use of gpio_pm_configure()	Subrata Banik
2019-05-11	soc/intel/cnl: Enable VT-d	John Zhao
2019-05-09	soc/intel/cannonlake: Fix pcie clock number	Lijian Zhao
2019-05-07	mb/google/sarien: Add SMBIOS type 9 fields	Lijian Zhao
2019-05-01	mb/google/sarien: Disable S5 wake on LAN by default	Eric Lai
2019-04-23	soc/intel/cannonlake: Enable PlatformDebugConsent by Kconfig	Kane Chen
2019-04-16	soc/intel/cannonlake: Configure Vmx support using Kconfig	Ronak Kanabar
2019-04-01	soc/intel/cannonlake: Add FSP UPD to unlock GPIO pads in devicetree	Krishna Prasad Bhat
2019-03-27	soc/intel/cannonlake: Configure voltage margining policies	Krzysztof Sywula
2019-03-21	soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports	Krishna Prasad Bhat
2019-03-16	soc/intel/cannonlake: Add required FSP UPD changes for CML	Subrata Banik
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-02-22	soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from device...	Jeremy Soller
2019-02-21	src/soc/intel/cannonlake: Add PsysPmax setting	Gaggery Tsai
2019-02-07	soc/intel/cannonlake: Add Whiskeylake SoC kconfig	Subrata Banik
2019-01-28	src/soc/intel/cnl/chip.h: Fix preprocessor condition	Angel Pons
2019-01-17	soc/intel/cannonlake: Change in SaGv options	Ronak Kanabar
2019-01-16	soc/intel/cannonlake: Add processor power limits control support	Sumeet Pawnikar
2019-01-08	soc/intel/cannonlake: Add FSP UPD for minimum assertion width	Duncan Laurie
2018-12-19	soc/intel/cannonlake: SATA and DMI power optimize	Lijian Zhao