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Some coreboot project code with my work
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src
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soc
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intel
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cannonlake
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fsp_params.c
Age
Commit message (
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Author
2019-02-22
soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from device...
Jeremy Soller
2019-02-21
src/soc/intel/cannonlake: Add PsysPmax setting
Gaggery Tsai
2019-02-13
soc/intel/cannonlake: Configure serial debug uart
Ronak Kanabar
2019-01-14
soc/intel/cannonlake: Provide interface to update TCC offset
John Su
2019-01-08
soc/intel/cannonlake: Add FSP UPD for minimum assertion width
Duncan Laurie
2019-01-01
soc/intel/cannonlake: Enable CNVi based on devicetree
Maulik V Vaghela
2018-12-19
soc/intel/cannonlake: SATA and DMI power optimize
Lijian Zhao
2018-12-19
soc/intel/cannonlake: Add Acoustic features
Lijian Zhao
2018-11-17
soc/intel/cannonlake: Add options for pcie ltr
Lijian Zhao
2018-11-05
soc/intel/cannonlake: Remove depreciated UPD selection
Lijian Zhao
2018-10-09
soc/intel/cannonlake: Disable Legacy PME for Root ports
Subrata Banik
2018-10-08
Move compiler.h to commonlib
Nico Huber
2018-10-04
soc/intel/cannonlake: Move the FSP related callbacks to separate files
Rizwan Qureshi