summaryrefslogtreecommitdiff
path: root/src/soc/intel/cannonlake/include
AgeCommit message (Expand)Author
2019-10-21Revert "soc/intel/cannonlake: Remove DMA support for PTT"Jeremy Soller
2019-08-15intel/smm: Define struct ied_header just onceKyösti Mälkki
2019-08-15soc/intel: Rename some SMM support functionsKyösti Mälkki
2019-08-15intel/ice,sky,cannon: Drop unused EMRR and UNCORE_EMRR codeKyösti Mälkki
2019-08-15mainboard/google: Fix indirect includesKyösti Mälkki
2019-08-09cpu/x86/smm: Drop SMI handler address from structKyösti Mälkki
2019-08-08arch/x86: Change smm_subregion() prototypeKyösti Mälkki
2019-08-07cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki
2019-07-25soc/intel: Guard remaining SA_DEV_ROOT definitionKyösti Mälkki
2019-07-21soc/intel: Expand SA_DEV_ROOT for ramstageKyösti Mälkki
2019-07-17soc/intel: Fix regression with hidden PCI devicesKyösti Mälkki
2019-07-13cpu/x86: Move smm_lock() prototypeKyösti Mälkki
2019-07-10soc/intel: Remove invalid smm_relocate stubsKyösti Mälkki
2019-07-07soc/intel/{cannonlake,icelake}: Do not define PCH_DEV_PMC in ramstageFurquan Shaikh
2019-07-07soc/intel/cannonlake, mb/google/sarien: Get rid of unused dev paramFurquan Shaikh
2019-07-05soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-HJeremy Soller
2019-07-04soc/intel: Replace uses of dev_find_slot()Kyösti Mälkki
2019-06-03soc/intel: Replace UART_BASE() and friends with a KconfigNico Huber
2019-05-28soc/intel/cannonlake: Dump ME status info before notify EndOfFirmwareBora Guvendik
2019-05-22soc/intel/cannonlake: Dump ME f/w version and status informationTim Wawrzynczak
2019-05-20soc/intel/cannonlake: Make use of gpio_pm_configure()Subrata Banik
2019-05-15soc/intel/cannonlake: Support different SPD read type for each slotPhilip Chen
2019-04-29soc/intel: Add GPI interrupt config register offset infoKarthikeyan Ramasubramanian
2019-04-29soc/intel/cannonlake: Modify dq_map to provide for 6 entriesPaul Fagerburg
2019-04-26soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS
2019-04-18soc/intel/cnl: Generate DMAR ACPI tableJohn Zhao
2019-04-11soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groupsAamir Bohra
2019-04-08Replace remaining IS_ENABLED(CONFIG_*) with CONFIG()Nico Huber
2019-03-29soc/intel/cannonlake: Ignore GBE LTRLijian Zhao
2019-03-25soc/intel/cannonlake: Clear PMCON status bitsKrishna Prasad Bhat
2019-03-16soc/intel/cannonlake: Add required FSP UPD changes for CMLSubrata Banik
2019-03-13soc/intel/cannonlake: Allow mainboard to override DRAM part numberFurquan Shaikh
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
2019-03-04soc/intel/cannonlake: Move common definitions to a header fileRizwan Qureshi
2019-02-27soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#Rizwan Qureshi
2019-02-27soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffersRizwan Qureshi
2019-02-26soc/intel/cannonlake: Update GPIO definitions for Virtual GPIORizwan Qureshi
2019-02-22soc/intel/cannonlake: Add ASL function for setting pad modeRizwan Qureshi
2019-02-21soc/intel/cannonlake: Add field to identify single channel memoryShelley Chen
2019-02-15soc/intel/cannonlake: Define VR settingsRoy Mingi Park
2019-02-07soc/intel/cannonlake: Configure GPIOs again after FSP-S is doneFurquan Shaikh
2019-01-25soc/intel/cannonlake: Export function to set After G3 stateDuncan Laurie
2019-01-16soc/intel/cannonlake: Add processor power limits control supportSumeet Pawnikar
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
2019-01-10soc/intel/common/block: Move tco common functions into block/smbusSubrata Banik
2019-01-09soc/intel/cannonlake: Enable/Disable IPU based on devicetree switchV Sowmya
2019-01-08soc/intel/cannonlake: Add chipset event loggingDuncan Laurie
2019-01-03soc/intel/cannonlake: Add cannonlake ACPI GPIO opLijian Zhao
2018-12-19soc/intel/cannonlake: Amend comment typoLijian Zhao