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path: root/src/soc/intel/cannonlake/include
AgeCommit message (Expand)Author
2019-06-03soc/intel: Replace UART_BASE() and friends with a KconfigNico Huber
2019-05-28soc/intel/cannonlake: Dump ME status info before notify EndOfFirmwareBora Guvendik
2019-05-22soc/intel/cannonlake: Dump ME f/w version and status informationTim Wawrzynczak
2019-05-20soc/intel/cannonlake: Make use of gpio_pm_configure()Subrata Banik
2019-05-15soc/intel/cannonlake: Support different SPD read type for each slotPhilip Chen
2019-04-29soc/intel: Add GPI interrupt config register offset infoKarthikeyan Ramasubramanian
2019-04-29soc/intel/cannonlake: Modify dq_map to provide for 6 entriesPaul Fagerburg
2019-04-26soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS
2019-04-18soc/intel/cnl: Generate DMAR ACPI tableJohn Zhao
2019-04-11soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groupsAamir Bohra
2019-04-08Replace remaining IS_ENABLED(CONFIG_*) with CONFIG()Nico Huber
2019-03-29soc/intel/cannonlake: Ignore GBE LTRLijian Zhao
2019-03-25soc/intel/cannonlake: Clear PMCON status bitsKrishna Prasad Bhat
2019-03-16soc/intel/cannonlake: Add required FSP UPD changes for CMLSubrata Banik
2019-03-13soc/intel/cannonlake: Allow mainboard to override DRAM part numberFurquan Shaikh
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
2019-03-04soc/intel/cannonlake: Move common definitions to a header fileRizwan Qureshi
2019-02-27soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#Rizwan Qureshi
2019-02-27soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffersRizwan Qureshi
2019-02-26soc/intel/cannonlake: Update GPIO definitions for Virtual GPIORizwan Qureshi
2019-02-22soc/intel/cannonlake: Add ASL function for setting pad modeRizwan Qureshi
2019-02-21soc/intel/cannonlake: Add field to identify single channel memoryShelley Chen
2019-02-15soc/intel/cannonlake: Define VR settingsRoy Mingi Park
2019-02-07soc/intel/cannonlake: Configure GPIOs again after FSP-S is doneFurquan Shaikh
2019-01-25soc/intel/cannonlake: Export function to set After G3 stateDuncan Laurie
2019-01-16soc/intel/cannonlake: Add processor power limits control supportSumeet Pawnikar
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
2019-01-10soc/intel/common/block: Move tco common functions into block/smbusSubrata Banik
2019-01-09soc/intel/cannonlake: Enable/Disable IPU based on devicetree switchV Sowmya
2019-01-08soc/intel/cannonlake: Add chipset event loggingDuncan Laurie
2019-01-03soc/intel/cannonlake: Add cannonlake ACPI GPIO opLijian Zhao
2018-12-19soc/intel/cannonlake: Amend comment typoLijian Zhao
2018-12-14soc/intel/cannonlake: Fix CNL-H GPIO pin mapDuncan Laurie
2018-11-27soc/intel/cannonlake: Delete unused macros in lpc.hSubrata Banik
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
2018-10-26soc/intel/cannonlake: Add back PM TIMER EMULATIONLijian Zhao
2018-10-17soc/intel/cannonlake: Add CNP PCH-H gpio pin definitionspraveen hodagatta pranesh
2018-10-17soc/intel/cannonlake: Add new cannon lake PCH-H supportpraveen hodagatta pranesh
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
2018-10-09soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devicesSubrata Banik
2018-10-09soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registersSubrata Banik
2018-10-08Move compiler.h to commonlibNico Huber
2018-10-04src/soc/intel/cannonlake: Fix IA32_PLATFORM_DCA_CAP addressElyes HAOUAS
2018-09-21soc/intel/cannonlake: Correct ITSS port id.praveen hodagatta pranesh
2018-09-20soc/intel/cannonlake: Remove const for spd_smbus_addressLijian Zhao
2018-08-30soc/intel/cannonlake: Update PMC base address for CNP H and LPMaulik V Vaghela