| Age | Commit message (Expand) | Author |
|---|
| 2021-03-27 | soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h | Subrata Banik |
| 2021-03-20 | soc/intel: Drop unused `GPIO_NUM_GROUPS` macro | Angel Pons |
| 2021-03-01 | soc/intel: Drop `bootblock_cpu_init()` function | Angel Pons |
| 2021-03-01 | soc/intel/{skl,cnl}: Do not chain-include systemagent.h | Angel Pons |
| 2021-03-01 | soc/intel: Drop `romstage_pch_init()` function | Angel Pons |
| 2021-03-01 | soc/intel: Factor out common smbus.h | Angel Pons |
| 2021-03-01 | soc/intel: Factor out common gpe.h | Angel Pons |
| 2021-02-25 | soc/intel/{skl,cnl}: Uniformize romstage.h whitespace | Angel Pons |
| 2021-02-16 | soc/intel: Drop aliases on MMCONF_BASE_ADDRESS | Kyösti Mälkki |
| 2021-01-24 | soc/intel/cnl: use Kconfig to determine PCH type | Michael Niewöhner |
| 2021-01-21 | soc/intel/cannonlake: Allow RP#1 usage for ClkSrc | Jeremy Soller |
| 2021-01-11 | soc/intel/cnl: add SLP_S0 residency register and enable LPIT support | Michael Niewöhner |
| 2020-12-17 | soc/intel/cannonlake: Change mainboard_silicon_init_params argument | Patrick Rudolph |
| 2020-12-04 | soc/intel/{skl,cnl}: add NMI_{EN,STS} registers | Michael Niewöhner |
| 2020-10-24 | {cpu,soc}/intel: deduplicate cpu code | Michael Niewöhner |
| 2020-10-21 | soc/intel: convert XTAL frequency constant to Kconfig | Michael Niewöhner |
| 2020-10-05 | soc: move mainboard_get_dram_part_num prototype to memory_info.h | Nick Vaccaro |
| 2020-10-05 | mb, soc: change mainboard_get_dram_part_num() prototype | Nick Vaccaro |
| 2020-10-03 | soc/intel: Make use of PMC low power program from common block | Subrata Banik |
| 2020-09-27 | soc/intel/cannonlake: Align gpio_op.asl with TGL | Subrata Banik |
| 2020-09-21 | src/soc/intel: Drop unneeded empty lines | Elyes HAOUAS |
| 2020-09-17 | soc/intel/cannonlake: add missing special function pads | Michael Niewöhner |
| 2020-09-17 | soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names | Michael Niewöhner |
| 2020-09-09 | soc/intel/cannonlake: Add PCIe ports on PCH-H | Patrick Rudolph |
| 2020-07-20 | soc/intel/cannonlake: Add configs for USB 3.1 Gen2 EV settings | Jamie Chen |
| 2020-07-14 | src: Remove unused 'include <stdint.h> | Elyes HAOUAS |
| 2020-06-25 | soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define | Edward O'Callaghan |
| 2020-05-26 | cannonlake: update processor power limits configuration | Sumeet R Pawnikar |
| 2020-05-14 | soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size() | Furquan Shaikh |
| 2020-05-14 | soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G | Furquan Shaikh |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-05-06 | treewide: replace GPLv2 long form headers with SPDX header | Patrick Georgi |
| 2020-05-06 | treewide: Move "is part of the coreboot project" line in its own comment | Patrick Georgi |
| 2020-05-02 | acpi: Move ACPI table support out of arch/x86 (3/5) | Furquan Shaikh |
| 2020-04-06 | soc/intel/cannonlake: Use SPDX for GPL-2.0-only files | Angel Pons |
| 2020-03-18 | soc: Remove copyright notices | Patrick Georgi |
| 2020-03-07 | intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers | Michael Niewöhner |
| 2020-03-07 | intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected | Michael Niewöhner |
| 2020-02-25 | soc/intel/cannonlake: Add TDC config for CML | Marx Wang |
| 2020-02-17 | src/intel: Define HFSTS3 register | Sridhar Siricilla |
| 2020-02-09 | soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC | Sridhar Siricilla |
| 2020-02-04 | soc/intel: Add get_pmbase | Eugene Myers |
| 2020-02-04 | soc/intel/cannonlake: Allow Audio DSP OSC qualification for low power idle | Aamir Bohra |
| 2020-01-18 | soc/intel/cannonlake: Add chip config for SATA strength | Jamie Chen |
| 2020-01-10 | soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper | Subrata Banik |
| 2020-01-09 | sb/intel/common: Add smbus_set_slave_addr() | Kyösti Mälkki |
| 2020-01-06 | soc/intel/cannonlake: Add VR config for CFL, CNL and WHL | Patrick Rudolph |
| 2019-12-26 | soc/intel/cannonlake: Refactor pch_early_init() code | Usha P |
| 2019-12-03 | soc/intel/cannonlake: Configure GPIO PM configuration in bootblock | Subrata Banik |
| 2019-11-22 | intel/smm: Provide common smm_relocation_params | Kyösti Mälkki |
