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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I48422453735d50eb9292f39a3c031073d647a17c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Add config to chip.h for tuning SATA gen3 strength.
BUG=b:147351936
BRANCH=none
TEST=build successful in puff
Change-Id: I4dcd23834fa3c01c1d88697a7bb8cf361709b62e
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38432
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch keeps required pch_early_init() function like ABASE programming,
GPE and RTC init into bootblock and moves remaining functions like TCO
configuration and SMBus init into romstage/pch.c in order to maintain only
required chipset programming for bootblock and verstage.
Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.
TEST=Able to build and boot hatch successfully.
Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This patch provides options to override descriptor default CPU flex
ratio from coreboot code. cpu_ratio_override to provide the required CPU
ratio.
Note: Don't override the flex ratio if cpu_ratio is 0.
BUG=b:142264107
TEST=Without override flex_ratio is 0 and verified booting to
OS after overriding with flex_ratio value 5.
Change-Id: Ib01650f52f3d402f669e7e7f5b28a648b86f08ec
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The devicetree is not made for user-choosable options, thus introduce
Kconfig options for both SGX and the corresponding PRMRR size.
The PRMRR size Kconfig has been implemented as a maximum value. At
runtime the final PRMRR size gets selected by checking the supported
values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest
to the chosen one.
When "Maximum" is chosen, the highest possibly value from the MSR gets
used. When a too strict limit is set, coreboot will die, printing an
error message.
Tested successfully on X11SSM-F
Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The filename chip.h has a special purpose with the generation
of static devicetree, where the configuration structure name matches
the path to the chip.h file. For example, soc/intel/skylake/chip.h
defines struct soc_intel_skylake_config.
The renamed file did not follow this convention and the structure it
defines would conflict with one defined soc/intel/common/chip.h if such
is ever added.
Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch includes common romstage code to setup the console
and load postcar.
Fix booting regression issue on all latest IA-SOC introduced by CB:34893
Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This timestamp also got unintentionally removed from some
boards as they were transformed to use common romstage entry.
Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34970
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Start with moving all postcar_frame related function
declarations here from <arch/cpu.h>.
Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0727a6b327410197cf32f598d1312737744386b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
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To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.
Replace this with method that relies on bus topology
that walks the root bus only.
Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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With VBOOT=y && VBOOT_MEASURED_BOOT=y message
digest will be allocated from the stack and
1 KiB reserve used with the recent platforms
was no longer sufficient.
The comment of LZMA scratchpad consuming stack
was obsolete for postcar, so these can be reduced
to same 4 KiB.
Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The DIMM manufacturing ID was not being initialized and so the DIMMs
were not described in SMBIOS tables properly.
The module type can also be provided, but the SMBIOS code expects
SPD module type values from DDR2 so the DDR3/4 values are adjusted
before sending to SMBIOS.
BUG=b:134897498
BRANCH=sarien
TEST=dump and compare with dmidecode
BEFORE:
Type: DDR4
Manufacturer: Unknown (0)
Form Factor: Unknown
AFTER:
Type: DDR4
Manufacturer: Hynix/Hyundai
Form Factor: SODIMM
Change-Id: Id673e08aa6e3dad196009c3c21a3dda2f40c9e42
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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What it really means to do is to use different FSP headers.
Change-Id: I3c75d4aac8525ab2639608fb9c1b3a9afef0e943
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This CL implements below changes:
1) Update FSP-M and FSP-S header files as per FSP release version 1155.
2) Update the PcdSerialIoUartNumber reference in fsp_params.c with
SerialIoUartDebugControllerNumber.
Change-Id: I6d412424f9f5c5d2d56b789c2fef4bdb817a3019
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32844
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ECC Support and VDD Voltage to dimm_info struct. Now Bus Width
and ECCSupport will be propagated correctly in SMBIOS Type 17 Entry.
Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33031
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fill the DIMM serial number field for SMBIOS from the saved SPD
data that is returned by FSP.
BUG=b:132970635
TEST=This was tested on sarien to ensure that SMBIOS type 17
filled the serial number from the DIMM:
Handle 0x000B, DMI type 17, 40 bytes
Memory Device
Locator: DIMM-A
Serial Number: 41164beb
Change-Id: I85438bd1d581095ea3482dcf077a7f3389f1cd47
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Enable VT-d through fsp upd VtdDisable. Update remapping structure
types in numerical order as all remapping structures of type 0 (DRHD)
enumerated before remapping structures of type 1 (RMRR), and so forth.
BUG=b:130351429
TEST=Booted to kernel and verified the DMAR table contents.
Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This change is mainly to control PlatformDebugConsent FSP UPD.
PlatformDebugConsent is enabled if SOC_INTEL_CANNONLAKE_DEBUG_CONSENT != 0.
PlatformDebugConsent in FspmUpd.h has the details.
BUG=b:130203864
TEST=boot ok and PlatformDebugConsent can be controlled by Kconfig
Change-Id: Ib845b5e42bc78fb352a0c97c6301f2aeca522f29
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32297
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Guckian
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This reverts commit 41dad286d846819242a84fc65faed2bbb35845ac. The change will make s0ix fail on Sarien/Arcada Platform.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I169bc6f41fba82fcf515267e8e1d08aa5ee2dce4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32391
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change VmxEnable UPD values based on Kconfig ENABLE_VMX
and remove it from Devicetree and chip.h
Remove Vmx dependency on Vt-d
Change-Id: I4180c2270038a28befd6ed53c9485905025a15ba
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32117
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch performs MP initialization by FSP using coreboot MP
PPI service.
BUG=b:74436746
TEST=Able to perform MP initialization on WHL and CML platform.
Change-Id: I530d50e5aacc3cb9b625df14a50d4c5923e3fb4d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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The following is the FSP logic: as long as the Cpu Ratio input in
coreboot is different with CpuStrapSet, system will force to follow
input from coreboot. But CpuStrapsetting is floating, it will be 0
from the first cold boot before memory training and set to 0x1c (or
max CPU ratio for the installed CPU) after first memory training.
The previous fix was attempting to ensure settings were cleared
when FSP was called in recovery mode, but only when coming from S5
which caused issues if recovery mode is requested by the OS and
is only followed by a warm reset.
BUG=b:129412691
TEST=Boot up sarien platform and force recovery, check there's no reset
in the path of recovery.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I959188be46343bc6f2cb3cc149097b4d449802aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32089
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures to make use of common MP Init Kconfig to
choose desire method to peform MP initialization for platform.
Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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coreboot have an option to use legacy UART or LPSS UART. FSP will use the
UART initialized by coreboot and we can choose an option to skip Uart
initialization by FSP.
For this, we need to pass correct debug interface flag to FSP through
which FSP will know which UART port to use. If we don't pass correct
interface information, FSP may try to dump logs on that port and it may
slow down the system.
BUG=none
BRANCH=none
TEST=Compile and boot with coreboot. Check FSP and coreboot logs are
coming on serial port.
Change-Id: I1ebb20c93e2c15ec085538509099de72bc9dd62c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In order to support mainboards that do not store DRAM part number in
the traditional way i.e. within the CBFS SPD for soldered memory, this
change provides a runtime callback to allow mainboards to provide DRAM
part number from a custom location e.g. external EEPROM on hatch.
For other boards it should be a NOP since the weak implementation of
mainboard_get_dram_part_num does nothing.
BUG=b:127609572
Change-Id: I9b2d4c33fc378b9a24b111971ec2bfdb5f8d57d0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31850
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This change moves soc_fill_power_state and soc_prev_sleep_state to
pmutil.c. It allows the functions to be used across romstage and smm.
BUG=b:124131938
BRANCH=none
TEST=none
Change-Id: If24c3feeb77f4fb692ef0bf38d537b2b54de3c36
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"mosys memory spd print all" returns incorrect memory ranks info.
This patch and 2 upcomming ones (one in FSP) will address the issue.
BUG=b:122329046
TEST=Boot to OS on Bobba variant of Octopus
BRANCH=octopus
Change-Id: I212215040e4786c258a9c604cc5c2bb62867c842
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Reviewed-on: https://review.coreboot.org/c/31235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: I72effa93e36156ad35b3e45db449d8d0d0cabf06
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This patch performs below tasks
1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.
2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.
3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.
* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC
4. Add correct FSP blobs path for WHL SoC based designs.
Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Disabling CpuRatio UPD for FSP will ensure it does not force a
hard reset to set the CPU Flex Ratio at boot. This is important
in a recovery mode boot where the SOC will lose power and need
to set the flex ratio again.
Disabling SaGv makes recovery mode training faster and mirrors
the setting that was done on Skylake.
BUG=b:123305400
TEST=reliably enter recovery mode on sarien
Change-Id: Ie9664493a980af9acce82faff81f4c4b1355be73
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc
code into common/block/smbus.
BUG=b:78109109
BRANCH=NONE
TEST=Build and boot KBL/CNL/APL/ICL platform.
Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/26166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This patch provides an option to enable or disable IPU (image processing unit),
* Add an entry for SA IPU in the pci_devs.h.
* Enable/Disable the IPU based on devicetree entry.
Change-Id: Ia155bc242dd33e816d056bbea1e3d4c1cbbe23da
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This structure is declared as a static CAR_GLOBAL in the common
PMC library code and in the SOC specific code. Remove the SOC
specific version and instead get the chipset_power_state pointer
from the PMC library.
This fixes events that were recorded in chipset_power_state at
boot but were reading as all zero when it was time to parse the
structure when logging events to flash.
Change-Id: I67a4f724c0707d98766ad28abd8d0b66a5615745
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Update HDAenable bit in Fsp memory init UPD data base on devicetree
settings.
BUG=N/A
TEST=N/A
Change-Id: I5159c00a855a2a9516714ccee8ee9933465c5063
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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CPU ratio will be fixed to non-turbo max value if CpuRatio UPD had been
set to zero.
BUG=N/A
TEST=Boot up into sarien system, cat /proc/cpuinfo and cpu frequency is
changing.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I3e82293c8b6027ddf9a528d0654fe46f233dcb82
Reviewed-on: https://review.coreboot.org/c/30216
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29302
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the SmbusEnable config option from devicetree and instead
use the state of the PCI device to determine if it should be
enabled or disabled.
Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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PCH ISH enabled/disabled in FSP memory init UPD, it will be match the
setting in ISH device on/off in devicetree.cb.
BUG=N/A
TEST=Build and pass on whiskey lake rvp platform.
Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities.
- Add gpio pin definitions for CNP-H and related changes.
- Add gpio device name, host software ownership reg offset for CNP-H.
BUG: none
TEST: build and flash, boot to windows and yocto os on both CFL RVP8 &
RVP11 and verify power management, IO device functionalities
work fine.
Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake
RVP8 platforms.
- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,
SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device.
- Add new device IDs to intel common code respectively.
- Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8.
- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c
is modified accordingly.
- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.
BUG=None
TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices
are enumerated and cross checked devices ids in serial logs and UEFI shell.
Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28718
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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