coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-08-23	soc/intel/cnl: Configure FSP option PcieRpSlotImplemented	Nico Huber
2020-08-18	elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE	Aaron Durbin
2020-08-12	soc/intel/cannonlake: Set FSP-M UPD Heci1BarAddress	Sridhar Siricilla
2020-08-10	soc/intel/cannonlake/acpi/serialio.asl: Don't advertise unavailable devices	Patrick Rudolph
2020-08-07	soc/intel/cnl: Set Heci1Disable depending on devicetree config	Felix Singer
2020-08-07	soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE	Subrata Banik
2020-08-05	{nb,soc}/intel: Use get_current_microcode_rev() for ucode version	Subrata Banik
2020-07-31	soc/intel/cannonlake: Fix DMAR when no iGPU is present	Patrick Rudolph
2020-07-28	soc/intel/cannonlake: Configure SataPwrOptEnable only if SATA is enabled	Felix Singer
2020-07-26	src: Update bare access to BOOL CONFIG_ vals to CONFIG()	Martin Roth
2020-07-26	cpu,soc/intel: Drop select SMP	Kyösti Mälkki
2020-07-26	src: Remove unused 'include <cbmem.h>'	Elyes HAOUAS
2020-07-22	soc/intel/cannonlake: Move tco_configure to bootblock	Tim Wawrzynczak
2020-07-21	src: Use ACPI macros	Elyes HAOUAS
2020-07-20	soc/intel/cannonlake: Add configs for USB 3.1 Gen2 EV settings	Jamie Chen
2020-07-14	src: Remove unused 'include <stdint.h>	Elyes HAOUAS
2020-07-06	soc/intel: Drop unused `#include <reg_script.h>`	Angel Pons
2020-07-01	soc/intel/cannonlake: make satahotplug user configurable via devicetree	Jonas Loeffelholz
2020-06-30	soc/intel/cannonlake: Add UWES ASL into xhci.asl	Edward O'Callaghan
2020-06-30	ACPI: Drop typedef global_nvs_t	Kyösti Mälkki
2020-06-30	src: Remove whitespaces before tabs	Elyes HAOUAS
2020-06-28	soc/intel/common: add TCC activation functionality	Sumeet R Pawnikar
2020-06-25	soc/intel/cannonlake: Add PchPmPwrCycDur to chip options	Sridhar Siricilla
2020-06-25	soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define	Edward O'Callaghan
2020-06-18	soc/intel/cannonlake: Enable FSP-S compression	Karthikeyan Ramasubramanian
2020-06-18	soc/intel: remove unused dptf.asl file and other defines	Sumeet R Pawnikar
2020-06-17	soc/intel/cannonlake/vr_config: Add CFL defaults to TDC powerlimit	Patrick Rudolph
2020-06-17	soc/intel/cannonlake: Use table instead of switch-case	Patrick Rudolph
2020-06-16	cpu/x86: Define MTRR_CAP_PRMRR	Kyösti Mälkki
2020-06-16	soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)	Kyösti Mälkki
2020-06-16	arch/x86: Create helper for APM_CNT SMI triggers	Kyösti Mälkki
2020-06-14	soc/intel/cannonlake/acpi: Capitalize hex number to unify with Skylake	Paul Menzel
2020-06-10	soc/intel/cannonlake: Put braces around else branch	Paul Menzel
2020-06-10	ACPI: Remove Kconfig COMMON_FADT	Kyösti Mälkki
2020-06-02	soc/intel/common/{pch,sata}: Remove SATA common code driver	Subrata Banik
2020-06-02	soc/intel/cannonlake: Add RP configuration settings	Christian Walter
2020-06-02	soc/intel/*/bootblock/cpu.c: Drop unused includes	Elyes HAOUAS
2020-06-02	src: Remove unused '#include <cpu/x86/lapic.h>'	Elyes HAOUAS
2020-05-28	soc/intel/common: Improve Type16 SMBIOS tables	Patrick Rudolph
2020-05-27	soc/intel/gma: Implement fsp_soc_get_igd_bar() in common code	Nico Huber
2020-05-27	soc/intel/gma: Move DDI-A 4-lane config to common code	Nico Huber
2020-05-27	soc/intel/gma: Move display and opregion init to common code	Nico Huber
2020-05-27	drivers/intel/gma: Move IGD OpRegion to CBMEM	Nico Huber
2020-05-26	cannonlake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-26	soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip options	Christian Walter
2020-05-26	intel/cannonlake: Implement PCIe RP devicetree update	Nico Huber
2020-05-18	src: Remove unused 'include <string.h>'	Elyes HAOUAS
2020-05-18	src: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-14	soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()	Furquan Shaikh
2020-05-14	soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G	Furquan Shaikh