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path: root/src/soc/intel/cannonlake
AgeCommit message (Expand)Author
2017-07-24Update files with no newline at the endMartin Roth
2017-07-24Fix files with multiple newlines at the end.Martin Roth
2017-07-22soc/intel/cannonlake: Keep variable from going out of scopeMartin Roth
2017-07-21Revert "soc/intel/cannonlake: Add postcar stage support"Martin Roth
2017-07-21Revert "soc/intel/cannonlake: Call into FSP siliconinit"Martin Roth
2017-07-21soc/intel/cannonlake: Call into FSP siliconinitLijian Zhao
2017-07-21soc/intel/cannonlake: Add postcar stage supportLijian Zhao
2017-07-20soc/intel/cannonlake: Make ramstage relocatableLijian Zhao
2017-07-19soc/intel/cannonlake: Add minimal changes to call FSP MemoryinitLijian Zhao
2017-07-19soc/intel/cannonlake: Add microcode supportLijian Zhao
2017-07-18soc/intel/cannonlake: Fix Build breakLijian Zhao
2017-07-18soc/intel/cannonlake: Use common GPIO driverAndrey Petrov
2017-07-18soc/intel/cannonlake: Add PMC headersAndrey Petrov
2017-07-17soc/intel/cannonlake: remove top_of_32bit_ram() declarationAaron Durbin
2017-07-13soc/intel/cannonlake: Add reset.cAndrey Petrov
2017-07-13soc/intel/cannonlake: Add MakefileAndrey Petrov
2017-07-13soc/intel/cannonlake: Add bootblock PCHAndrey Petrov
2017-07-13soc/intel/cannonlake: Add early CPU initializationAndrey Petrov
2017-07-12soc/intel/cannonlake: Add PCI dev macros and IDsAndrey Petrov
2017-07-12soc/intel/cannonlake: Add report_platform.cAndrey Petrov
2017-07-02soc/intel/cannonlake: Add bootblock.cAndrey Petrov
2017-06-29soc/intel/cannonlake: Add UART initializationAndrey Petrov
2017-06-29soc/intel/cannonlake: Add initial dummy directoryLijian Zhao