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2017-12-20soc/intel/cannonlake: Tell FSPM UART port numberLijian Zhao
Cannonlake FSP will send debug message on selected UART port, use same coreboot UART debug port to FSP. TEST=Boot up with board have UART port 0 and can see the print of FSP Change-Id: Id72e459d2fbb1f16b005d22fac66667086880384 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-16soc/intel/common/fast_spi: implement spi_flash_ctrlr_protect_region()Aaron Durbin
In the fast spi support implement the callback for flash_protect(). This removes the need for having SOC_INTEL_COMMON_SPI_FLASH_PROTECT Kconfig option as well spi_flash_get_fpr_info() and separate spi_flash.[ch]. BUG=b:69614064 Change-Id: Iaf3b599a13a756262d3f36bae60de4f7fd00e7dc Signed-off-by: Aaron Durbn <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-14soc/intel/cannonlake: Fix UART2 serial log broken issueSubrata Banik
Cannonlake rvp serial log has been regressed with commit I7eea910e065242689e87adac41281131674b39af(soc/intel/cannonlake: Clean up UART code) because of common UART code is unable to link all __weak function implementation from SoC uart.c due to existing macro #define __SIMPLE_DEVICE__. Hence UART2 PCI device resource programming is different than what it's been programmed before. This patch ensures UART2 PCI device resource enumeration is working and we are getting serial log as expected. Change-Id: I1f9df5e8d6490090ed65b06bdd0b40f824d36a8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22862 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-13src/soc/intel/cannonlake: Add _PRW for CNViBora Guvendik
Add _PRW so that wake on WLAN feature works. TEST=Boot to OS and check if WLAN device wakes host. Change-Id: Id6689754d1c4100615e4e4ae5a7f9846f4bf785f Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-12-11soc/intel/cannonlake: Add support for D0 steppingLijian Zhao
D0 stepping with CPUID 0x60663 need to be added in coreboot. TEST=Boot up with D0 stepping processor Change-Id: I3b0f2616843367d2bfbee1b5bf75772b9e83e931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-09soc/intel/cannonlake: Clean up UART codeAamir Bohra
Clean up and move UART related code under a single uart.c file. Change-Id: I7eea910e065242689e87adac41281131674b39af Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-08soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.cSubrata Banik
This patch ensures that all required information for pch/mch/igd deviceid and revision are available in single stage and makes use of local references. TEST=Build and boot cannonlake_rvp to get PCH information as below PCH: device id xxxx (rev xx) is Cannonlake-Y Premium Change-Id: I420e94043145e8a5adcf8bb51239657891915d84 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07soc/intel/cannonlake: Make use of Intel common Graphics blockSubrata Banik
TEST=Build and boot cannonlake rvp. Change-Id: Iaa1314ae3fcb4a8a3b55a314e79511f5dcba163d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-05soc/intel/cannonlake: Fix DSX_CFG macro name for AC_PRESENTFurquan Shaikh
DSX_CFG provides a config option to disable internal pull-down on AC_PRESENT. This change updates macro name to reflect this correctly. Change-Id: I620d7da4048178f86de41f3afd98543cf8efc5ce Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-02soc/intel/cannonlake: Initialize PMC controllerSubrata Banik
PMC controller gets hidden during FSP-Silicon initialization using sideband interface on CannonLake platform. Hence accessing PWRMBASE using PCI config space will return invalid BAR value as 0xFFFFF000. Also PMC PCI driver will not be able to initialize PMC controller as its not showing over PCI bus. coreboot PCI enumeration log shows: PCI: Static device PCI: 00:1f.2 not found, disabling it. This patch ensures PMC controller is getting initialized using boot state machine right after FSP Silicon Init returns (BS_DEV_INIT_CHIPS/ BS_ON_EXIT). TEST=Ensures PWRMBASE address is 0xFE000000 and PMC controller is getting initialized during BS_DEV_INIT_CHIPES/BS_ON_EXIT. Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-23soc/intel/cannonlake: Add PM methods to power gate SD card controllerVaibhav Shankar
When system enters S0ix, system fails to power gate SD card controller. This patch implements PM methods to put the SD card controller in D3 during S0ix entry. TEST=Suspend and resume using 'echo freeze > /sys/power/state'. The System should not be blocked by sd card controller. Change-Id: I9a9fe14fb6cd3b76ee95c565b3359cdae1a3c445 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/22487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-23soc/intel/cannonlake: Invoke pmc and hard reset only if CSE fails to resetJohn Zhao
If CSE fails to do a global reset with the calling sequence of heci reset/send/receive, then invoke pmc and hard reset. TEST= Force global reset from early or late romstage. The function send_heci_reset_message has the calling sequence of heci reset/send/receive. It is observed timed out error (associated with heci_receive) occurs only if global reset is forced during early romstage. If global reset is trigged at late stage (i.e, after fsp_memory_init), then no timed out error and CSE handles reset properly. Change-Id: I5bb12554e5745d7704a1b684a3a51034bb35f787 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22549 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-20soc/intel/cannonlake: Add ACPI workaround for EMMCLijian Zhao
Two W/A had been added here for EMMC to make it working properly. 1. Enable power gating after D3 entry, disable power gating before D0 entry. 2. Add 50 ms delay to ensure Rcomp calibration done before EMMC out of D3. BUG=b:69323943 TEST=Run multiple ACPI S3 cycles on cannonlake u LPDDR4 platform. Change-Id: Ic6e98264521fb02b911a8c157a7982afa35fe20c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-17soc/intel/cannonlake: fix gpio pin numbersBora Guvendik
Update pin numbers to match kernel cannonlake pinctrl driver. TEST=boot to OS Change-Id: Id65736db03200fd434dd9292ce081727abd6832b Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22477 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17soc/intel/cannonlake: Add cpu.asl fileShaunak Saha
This patch adds the cpu.asl file in cnl. We are only defining the PNOT method here in this patch as this is needed by the ec/google/chromeec/acpi/ec.asl file for the AC methods. TEST= code compiles and boots when we include the ec.asl file. Change-Id: Id93012833fac116d4d7514aa2d0b8493d2f666a9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-11-15soc/intel/cannonlake: Fix and clean up xhci ACPI codeVaibhav Shankar
During S3 cycling, system entered S3 only once and falied to enter S3 the second time. The system gets stuck at this point and we have to do a cold reboot to restore the system. Since XHCI IP is able to power gate during kernel freeze/suspend, this patch removes unnecessary device gating from ASL. This helps in continuous cycling of S3. BUG=b:69115421 TEST=run powerd_dbus_suspend multiple times and check if the system enters and resumes from S3. Change-Id: Id459631ea2d32feea4b8f658fd34fa25945f909e Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/22389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13soc/intel/cannonlake: Define default LPSS clockLijian Zhao
Default LPSS clock need to be defined for SOC. TEST=Turn on COMMON_I2C_DEBUG, add I2C clock entry and check I2C programing properly during coreboot. Change-Id: I2c6b9bb23950b09f6f05e3ef762ccb1a260efc5f Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11soc/intel/cannonlake: Make use of Intel SPI common blockSubrata Banik
TEST=Build and boot RVP Change-Id: I5ff9867f08e43016a797b1b3719053df0c382174 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11soc/intel/{cannonlake,skylake}: Add _soc_ prefix in spi soc routineSubrata Banik
This ensures that function callback into the SoC code. Change-Id: Idc16d315ba25d17a2ab537fcdf0c2b51c8802a67 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10soc/intel/cannonlake: Remove structure variable initialization with 0Subrata Banik
Variable without an initializer will default to 0 hence no need of an explicit initialization. Change-Id: I208d5e475600b102cd3d972919b170c10c790b32 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-04soc/intel/cannonlake: Add DSP supportLijian Zhao
Add dsp driver support for cannonalake, especially the scan_bus function of Audio controller required. TEST=N/A Change-Id: I573fecedbd4d6619112765c3f2f8baccabeb5ac5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2017-11-04soc/intel/cannonlake: Install common i2cLijian Zhao
Add common i2c support for cannonlake. TEST=N/A Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22238 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04sb and soc: Enforce correct offset of member "chromeos" in global_nvs_tJonathan Neuschäfer
The padding has recently been broken in commit 90ebf96df5 ("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset for chromeos"). Avoid this bug in the future. Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-01soc/intel/cannonlake: Use SCS common codeBora Guvendik
This patch uses common SCS library to set up sd card. Change-Id: I7978bebaeba3a04fbfd01b3a5e5a37af61d2f4ce Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-27soc/intel/cannonlake: Use common p2sb driverLijian Zhao
Add common p2sb driver support. TEST=Boot up into OS and read back pcr mmio address by iotools, return is not 0xffffffff. Change-Id: Ida66663e6daabfcb94d7e3224d75b118fc7cf829 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-26soc/intel/cannonlake: Add support for C state and P stateShaunak Saha
This patch adds the C state and P state configurations for cannonlake soc. TEST = Boot and test the CPU states for all the cores are present in "powertop" tool output. Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/21891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-26soc/intel/cannonlake: remove duplicate power_state migrationPatrick Georgi
Common PMC code comes with its own. Change-Id: Ic055f046a2da1c56af4cc7936602d6191ffe7eef Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-23soc/intel/cannonlake: Increase stack size from 4KiB to 8KiBJohn Zhao
Backtracking stack used BEFORE each function call: 1. cbfs_boot_locate(&file_desc, "vbt.bin", NULL): 4104 (stack overrun) 2. locate_vbt: 4068 3. vbt_get: 4036 4. platforms_fsp_silicon_params_cb: 3924 5. do_silicon_init(&fsps_hdr): 3684 (3684-1092=2592 due to fsps) 6. fsp_silicon_init: 1092 Increase the stack size from 4kiB to 8kiB to prevent stack overrun. TEST=No stack overrun is observed and it boots to OS properly. Change-Id: I7e458b4489cea32449f197621ec81009ea7dd0bd Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21977 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22soc/intel/cannonlake: Change max root port to 16Lijian Zhao
Cannonlake SOC support up to 16 PCI express root port. BUG=CID 1381813;1381814; Change-Id: I4df610e3fb01bd8e62be7e9c62144125f2a96c25 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-20soc/intel/cannonlake: Add platform.aslLijian Zhao
Include common platform.asl to have generic indication of power transition state of system. TEST=Enter and resume from S3, check the post code had been changed to 0096 and 0097. Change-Id: Ic38ac6d7e60441caeba5c088c9dbe4d901355782 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22111 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-19soc/intel/cannonlake: Fix HECI error on resetLijian Zhao
Move HECI init from bootblock to romstage, the HECI bar saved by CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage will be read back from PCI. Also add fail safe option to reset in case of HECI command not successful. TEST= Force global reset from FSP and read back HECI bar in debug print. Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19soc/intel/cannonlake: Use EBDA structure to store soc reserve memory sizeSubrata Banik
Avoid calling calculate_dram_base() function to get chipset reserved memory size during pci resource allocation. Rather use EBDA to store chipset reserved memory size while calling cbmem_top_int(). This patch avoids one extra calculate_dram_base() call. BRANCH=none BUG=b:63974384 TEST=Ensures DRAM based resource allocation has taken care of Intel SoC reserved ranges. Change-Id: I2771ea55253ca7d16cd2e2951889ab092b47a9b1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22099 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-19soc/intel/cannonlake: Add IGD Support and pre-OS display codeAbhay Kumar
1. Add IGD opregion initialization. 2. Use frame buffer return by FSP for display. 3. Derived from "src/soc/intel/apollolake/graphics.c" with changes needed for CNL. TEST=Pre-OS screen comes up and VBT is getting passed to kernel. Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/21999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-18soc/intel/cannonlake: Set platform Debug Probe TypeLijian Zhao
Add option for user to select what kind of probe can be used for platform debug. TEST=Set to XDP and boot up system with XDP hooked, able to halt. Change-Id: Ib6add93e3f1c8a646aa625a4cea9be0acecc0487 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21942 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-18soc/intel/cannonlake: Update PCIE CLKREQ programingLijian Zhao
UPD of PCI express clock request was updated in FSP 7.0.14.11, change that in coreboot accordingly. TEST=NONE Change-Id: I2261deccfb489c0de577d580997744a484f07a04 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21878 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-18soc/intel/cannonlake: Add finalize functionLijian Zhao
Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-18soc/intel/cannonlake: Calculate soc reserved memory sizeSubrata Banik
This patch implements soc override function to calculate reserve memory size (PRMRR, ME stolen, PTT etc). System memory should reserve those memory ranges. BRANCH=none BUG=b:63974384 TEST=Ensures DRAM based resource allocation has taken care of intel soc reserved ranges. Change-Id: I3052a255c4496dc81c8dfc6882d3ad504abae9c6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18soc/intel/cannonlake: Use EBDA area to store cbmem_top addressSubrata Banik
This patch uses BIOS EBDA area to store relevent details like cbmem top during romstage after MRC init is done. Also provide provision to use the same EBDA data across various stages without reexecuting memory map algorithm. BRANCH=none BUG=b:63974384 TEST=Ensures HW based memmap algorithm is executing once in romstage and store required data into EBDA for other stage to avoid redundant calculation and get cbmem_top start from EBDA area. Change-Id: I763ad8181396ea8d8c0d5cf088264791ba62dceb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18soc/intel/cannonlake: Refactor memory layout calculationSubrata Banik
This patch split entire memory layout calculation into two parts. 1. Generic memory layout 2. SoC specific reserve memory layout. usable memory start = TOLUD - Generic memory size - - soc specific reserve memory size. Change-Id: I56e253504a331c0663efb2b90eaa0567613aa508 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18soc/intel/cannonlake: Create acpi_get_sleep_type() to get previous sleep stateSubrata Banik
This patch uses PMC common function to get previous sleep state using cbmem or chipset_power_state global structure. acpi_get_sleep_type is needed in PRE_RAM stage when soc selects CONFIG_EARLY_EBDA_INIT kconfig option. Change-Id: Ib9f8bdc1c682807450b6c01941b9a0927789b2d8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-12soc/intel/common: Clean up PMC library GPE handling APIFurquan Shaikh
1. Update gpe handling function names to explicitly mention if they are operating on: a. STD GPE events b. GPIO GPE events c. Both 2. Update comment block in pmclib.h to use generic names for STD and GPIO GPE registers instead of using any one platform specific names. BUG=b:67712608 Change-Id: I03349fe85ac31d4215418b884afd8c4b531e68d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21968 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12soc/intel/cannonlake: add length information for communitiesBora Guvendik
TEST = Boot to OS, check if pinctrl probed successfully Change-Id: Ib20c955d535cd9c48175b4d3934b4699b6186874 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-12soc/intel/cannonlake: Add ACPI platform sleep capabilityVaibhav Shankar
Add the required ACPI sleep states Change-Id: I7750062554f087e4f88da56790e4122d5fa20529 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/21975 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-11soc/intel/cannonlake: Change default UART number to 2Lijian Zhao
Set default UART number to 2 if 32bit PCI got selected, the proper debug print can be seen from serial port in case of switch between platforms, especially when change to lpss uart from legacy uart or vise versa. Change-Id: If2e0e8c8ac86e49a245f3d1d4722d40be9c01e25 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21544 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-09soc/intel/*lake: Load vbt when it's neededPatrick Georgi
That removes the need for another global variable. Change-Id: I25e12ba724836de4c8afb25cd347cafe6df8cea9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21907 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06soc/intel/common: refactor locate_vbt and vbt_getPatrick Georgi
Instead of having all callers provide a region_device just for the purpose of reading vbt.bin, let locate_vbt handle its entire life cycle, simplifying the VBT access API. Change-Id: Ib85e55164e217050b67674d020d17b2edf5ad14d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21897 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06soc/intel/cannonlake: Enable MRC cacheLijian Zhao
Enable MRC cache by default. TEST=Warm reset and check coreboot serial log, MRC related log can be seen. Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06soc/intel/cannonlake: reduce bootblock sizeAaron Durbin
Reduce the bootblock size to 16KiB from the default 64KiB. Not all that space is necessary. Change-Id: I5c15d0af0f85282b84c8983f0a015aeb45c00a07 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-05soc/intel/cannonlake: Add all the SOC level DSDT tablesLijian Zhao
Add all the SOC level DSDT tables, reference from skylake/kabylake. Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-18 02:25:34 +0000