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2019-08-15soc/intel: Rename some SMM support functionsKyösti Mälkki
Rename southbridge_smm_X to smm_southbridge_X. Rename most southcluster_smm_X to smm_southbridge_X. Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15intel/ice,sky,cannon: Drop unused EMRR and UNCORE_EMRR codeKyösti Mälkki
There was no code present to call wrmsr with the data we prepared in the structs. The MSRS are already set up by FSP, just reference with the more recent names of PRMRR and UNCORE_PRMRR. Change-Id: Ib49e7af52e1170a1304975ff0ae63f99e106dffe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15soc/intel: Drop spurious includesKyösti Mälkki
Change-Id: I2fff107e38abdd34f2d80d4d258be4c429d371e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15mainboard/google: Fix indirect includesKyösti Mälkki
Change-Id: Ie79702efab519b16cff45ccad61b95e7d8c2fbac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34854 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15cpu/x86/smm: Define single smm_subregion()Kyösti Mälkki
At the moment we only have two splitting of TSEG, one with and one without IED. They can all use same implementation. Make configuration problems of TSEG region assertion failures. Rename file from stage_cache.c to tseg_region.c to reflect it's purpose. Change-Id: I9daf0dec8fbaaa1f4e6004ea034869f43412d7d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34776 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13cpu/x86: Separate save_state struct headersKyösti Mälkki
Any platform should need just one of these. Change-Id: Ia0ff8eff152cbd3d82e8b372ec662d3737078d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34820 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-11arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki
It is easier to track CAR_GLOBAL_MIGRATION which is the approach to be deprecated with the next release. This change enforces new policy; POSTCAR_STAGE=y is not allowed together with CAR_GLOBAL_MIGRATION=y. Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-11arch/x86: Enable POSTCAR_CONSOLE by defaultKyösti Mälkki
Almost all platforms force it on. Make it enabled by default but under user control to optionally disable it. Change-Id: I6b0f19c8bfd6ffed93023d57a1d28ca6acc06835 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09cpu/x86/smm: Drop SMI handler address from structKyösti Mälkki
Change-Id: Ib925b11ba269e0f3a9a0a7550705bf2a6794c5b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-09soc/intel: Drop pmc_soc_restore_power_failure()Nico Huber
Get rid of this function and its dangerous, weak implementation. Instead, call pmc_set_power_failure_state() directly from the SMI handler. Change-Id: I0718afc5db66447c93289643f9097a4257b10934 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/intel/{cnl,icl}: Use new power-failure-state APINico Huber
pmc_soc_restore_power_failure() is only called from SMM, so add `pmc.c` to the `smm` class. Once all platforms moved to the new API, it can be implemented in a central place, avoiding the weak- function trap. Change-Id: Ib13eac00002232d4377f683ad92b04a0907529f3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34726 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08soc/intel: Fix SMRAM base MSRKyösti Mälkki
Previous setting was correct but assumed SMI handler is always located at the beginning of TSEG. Break the assumption. Change-Id: I5da1a36fc95f76fa3225498bbac41b2dd4d1dfec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34730 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/x86: Handle smm_subregion() failureKyösti Mälkki
The callers don't necessarily check return value of function. Make sure the parameters are not left uninitialised in that case. Change-Id: Ic02db2d35b2ec88506320e7df609940de4aef005 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34708 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/x86: Change smm_subregion() prototypeKyösti Mälkki
Do this to avoid some amount of explicit typecasting that would be required otherwise. Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-08lib/stage_cache: Refactor Kconfig optionsKyösti Mälkki
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE. Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache. There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE. As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option. Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki
No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07intel/icelake,skylake,cannonlake: Drop unused parameterKyösti Mälkki
Change-Id: I0900c3b893d72063cc8df5d8ac370cf9d54df17a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-05soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOCAamir Bohra
This implementation adds support to provide list of LPSS controllers for a canonlake and icelake platforms. It implements strong function of get_soc_lpss_controllers defined under intel common block lpss driver. Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-05soc/intel/cnl/graphics: Hook up libgfxinitNico Huber
Change-Id: Ic038adad6cf76867cd4a8626d4c49e17018389fd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-04soc/intel/common/block/uart: Update the UART PCI device referenceAamir Bohra
This implementation revises the UART PCI device reference in common UART driver. The SOC functions have been aligned to provide the UART PCI device reference using pcidev_path_on_root. The uart_get_device() return type is changed, and files in which it gets used are updated. Change-Id: Ie0fe5991f3b0b9c596c3de9472e98e4091d7dd87 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-02soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabledAamir Bohra
Add a check to enable ACPI timer emulation only when the APCI PM timer is disabled. Change-Id: I21c0b89218d0df9336e0b0e15f1b575b8508fb96 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-08-02soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usageSubrata Banik
This patch overrides EnableTcoTimer FSP UPD default value based on PmTimerDisabled coreboot devcietree config. BRANCH=none BUG=b:138152075 Change-Id: I347c15c7b65fb4c19b9680f127980d4ddab8df51 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-08-02soc/intel/common/pch: Move thermal kconfig selection into common/pchSubrata Banik
This patch moves SOC_INTEL_COMMON_BLOCK_THERMAL selection from respective soc/intel/{skl/cnl/icl} to common/pch/Kconfig. Change-Id: I7c9c8a87cfc5cb4c2fa8b215e56cc35c1f0cce28 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34650 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-01soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registersDavid Wu
Clear the GPI Interrupt Status & Enable registers to prevent any interrupt storms due to GPI. BUG=b:138282962 TEST=Ensure that the Interrupt status & enable registers are reset during the boot-up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS. Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-31soc/intel/cannonlake: Enable FSP to use coreboot stack for cometlakeAamir Bohra
FSP v1263 for CML supports FSP to use coreboot stack. This change selects common stack config, that enables coreboot to support share stack with FSP. BUG=b:133398276 Change-Id: I4098a4374363ca6f3c86c396d097f9eabc9a28fe Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34130 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ixSumeet Pawnikar
Enable PCH thermal sensor for dynamic thermal shutdown for S0ix state. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE. Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34522 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-30soc/intel/cnl: Only print ME status one timeTim Wawrzynczak
There were two hooks in the boot state machine which dumped the ME status to the debug UART, which is unnecessary. Removed the hook for the BS_OS_RESUME_CHECK state, leaving just BS_PAYLOAD_LOAD, which is called before FspNotifyEndOfFirmware, as required. BUG=b:138463532 BRANCH=none TEST=Boot up, check cbmem to ensure the ME status messages are only printed one time. Change-Id: I86bc6e33de4096f33023730ffabb25715c985de0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-30soc/intel/cannonlake: Allow coreboot to handle required chipset lockdownSubrata Banik
This patch disables FSP-S chipset lockdown UPDs and lets coreboot perform chipset lockdown in ramstage. BUG=b:138200201 TEST=FSP debug build suggests those UPDs are disable now. Change-Id: I7e53c4e4987a7b0e7f475c92b0f797d94fdd60f4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-30soc/intel/cannonlake: Add new PCI IDsFelix Singer
* PCH IDs: H310, H370, Z390, B360, C242, HM370 * IGD IDs: Another variant of UHD-Graphics 630 * MCH/CPU IDs: Used at i3-8100 Used documents: * 337347-005 TESTED=Gigabyte Z390M Gaming Change-Id: I5be88ef23359c6429b18f17bcffbffb7f10ba028 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34600 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-30soc/intel/{broad,cannon,sky}: Fix possible out-of-bounds readsJacob Garber
There will be a possible out of bounds array access if power_limit_1_time == ARRAY_SIZE(power_limit_time_sec_to_msr), so prevent that in the index check. This issue was fixed for other cpus in commit 5cfef13f8d (cpu/intel: Fix out-of-bounds read due to off-by-one in condition). Based on the discussion for that commit, also remove the magic constant 28 in favour of the index of the last array element. Change-Id: Ic3f8735b23a368f8a9395757bd52c2c40088afa1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229673 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-29soc/intel/cannonlake: Correct the data type of serial_io_devAamir Bohra
Change-Id: Id974a4bb84b7d5caddece04f93bf4e830d15b576 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34466 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25soc/intel: Guard remaining SA_DEV_ROOT definitionKyösti Mälkki
Prevent implicit cast to pointers. The compiler doesn't warn about the conversion from integer to pointer without a cast, because SA_DEV_ROOT is literally '0' and there seems to be an exception for that conversion. Change-Id: I64fc156e3b9f578414ad03a00edb7cf3e33205c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-25soc/intel/cannonlake: Split the "internal PME" wake-up into more detailPaul Fagerburg
The "internal PME" wake-up source could be from integrated LAN, HD audio/audio DSP, SATA, XHCI, CNVi, or an ME maskable host wake. chromium:1680839 adds USB port details to the wake-up when the XHCI causes the wake-up. Expand the logging for wake-up details to identify and log the other wake-up sources with more details. Note that wake on Integrated LAN (GbE), SATA, and ME Maskable Host Wake are not in use on Hatch, so these will not be tested. BUG=b:128936450 BRANCH=none TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` Ensure /build/hatch/firmware/image-hatch.serial.bin has been built. Program image-hatch.serial.bin into the DUT using flashrom. Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via servo). XHCI USB 2.0 * Plug a USB keyboard into a USB-A port * ``powerd_dbus_suspend`` * Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. * Press a key on the USB keyboard * ``mosys eventlog list`` shows: 12 | 2019-06-26 14:52:23 | S0ix Enter 13 | 2019-06-26 14:53:07 | S0ix Exit 14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3 15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109 CNVi (connected to Wi-Fi): * Enable wake on disconnect via ``iw phy0 wowlan enable disconnect`` * Set up a hotspot on an Android phone * Connect the Chromebook to th hotspot * ``powerd_dbus_suspend`` * Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. * Turn off the hotspot on the phone * ``mosys eventlog list`` shows: 8 | 2019-07-11 10:58:17 | S0ix Enter 9 | 2019-07-11 10:59:17 | S0ix Exit 10 | 2019-07-11 10:59:17 | Wake Source | PME - WIFI | 0 11 | 2019-07-11 10:59:17 | Wake Source | GPE # | 109 XHCI USB 3.0 * TBD HD Audio * TBD Change-Id: I2c71f6a56b4e1658a7427f67fa78af773b97ec7f Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34289 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21soc/intel: Expand SA_DEV_ROOT for ramstageKyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21soc/intel: Fix chip_info for PCH_DEV_PMCKyösti Mälkki
Since PCH_DEVFN_PMC device is a PCI device that may be hidden from enumeration, use SA_DEVFN_ROOT instead to locate the SOC configuration. Change-Id: I4b5195827fb32ec1dbd0bd6c9e243f4f9a4775ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-19soc/intel/common: Add SOC specific function to get XHCI USB infoKarthikeyan Ramasubramanian
It feels appropriate to define SoC specific XHCI USB info in SoC specific XHCI source file and an API to get that information instead of defining it in elog source file. This will help in other situations where the information is required. BUG=None BRANCH=None TEST=Boot to ChromeOS. Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34290 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18soc/intel: Use config_of()Kyösti Mälkki
Change-Id: I0727a6b327410197cf32f598d1312737744386b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian
2019-07-18soc/intel: Use config_of_path(SA_DEVFN_ROOT)Kyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I53324603c9ece1334c6e09d51338084166f7a585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-17soc/intel/cannonlake: Add device Ids for new CFL SKUs supportLean Sheng Tan
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs - Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246 - Make some minor alignments & naming corrections to align with the rest TEST= build, boot to both Linux & windows OS on CFL H & S platforms and verified all the device Id's in serial console logs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-17soc/intel: Fix regression with hidden PCI devicesKyösti Mälkki
Fix regression with commit 903b40a soc/intel: Replace uses of dev_find_slot() Platforms where FSP hides PCI devices before enumeration may halt with error message 'PCI: dev is NULL!'. The workaround here is to print an error message revealing the faulty source code function and revert to old behaviour of dev_find_slot(). Change-Id: I5eab3e7f1993b686103eaa257aacda379dc259fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34285 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16soc/intel/{cnl,icl}: Always use CAR NEM enhanced by defaultAngel Pons
The FSP_CAR option has additional configuration options whose default values result in boot failures. Since default values should always boot, default to the open-source CAR NEM Enhanced implementation instead. This also allows us to get rid of an unnecessary vendor-specific special case. Change-Id: I30b1808f91701c07dce6f1de08c213150e8a675a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34287 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-15intel/cannonlake: Fix indentationKyösti Mälkki
Change-Id: Ia3ec5fbdbbf2712fe314909e05aab1b135534630 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-13soc/intel/cannonlake: Remove unused header files from southbridge.aslAamir Bohra
Change-Id: I1f970db22f87e8eba0129ca049f75d16539644a5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-13cpu/x86: Move smm_lock() prototypeKyösti Mälkki
The function implementations are in local platform scopes. Change-Id: I7a3025398b15fe6d2c5a13cdb65f3e62a49c0bc6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34151 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSPNico Huber
We got rid of the dangerous reconfiguration of arbitrary pads in coreboot, but FSP still overrode that. Make sure that it doesn't enable a UART for debug output when it isn't configured in core- boot. This, again, shows how dangerous it is to leave any FSP UPD at its binary default. Change-Id: I7280a80f71ddddbe78352eb696e6f5844d2df0b2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-12soc/intel/common: Add Coffee Lake H 6+2 Xeon graphics idNico Huber
Change-Id: Ibf72a8db2e4292e5d5bb67b8778e1d1ebfa19632 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34164 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12soc/intel/common: Add CM246 LPC device idNico Huber
Change-Id: Ic57ccf48988afbbba256172a7540bb02b88d1bbd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34163 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11soc/intel/cannonlake: Add GPID and CGPM methods to GPIO ASLTim Wawrzynczak
The GPID method returns the PCR Port ID of the given GPIO community. The CGPM method alters the given GPIO community's PM bits, given in Arg1. Change-Id: I098ee08573eb4f8a45d9b5ae84f2d85ce525c9b8 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11soc/intel/cannonlake: Make EC S0ix notification optional in LPITTim Wawrzynczak
Only call the \_SB.PCI0.LPCB.EC0.S0IX method if it exists. Change-Id: Idf465f8ad7cb016f3ad3d9710b46e35f66f8939b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-11soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timerSubrata Banik
This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer for better code sharing. Also ported CB:33512 for SPT and ICP PCH. Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 07:02:01 +0000