coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-08-08	soc/intel: Fix SMRAM base MSR	Kyösti Mälkki
2019-08-08	arch/x86: Handle smm_subregion() failure	Kyösti Mälkki
2019-08-08	arch/x86: Change smm_subregion() prototype	Kyösti Mälkki
2019-08-08	lib/stage_cache: Refactor Kconfig options	Kyösti Mälkki
2019-08-07	cpu/x86/smm: Promote smm_subregion()	Kyösti Mälkki
2019-08-07	intel/icelake,skylake,cannonlake: Drop unused parameter	Kyösti Mälkki
2019-08-05	soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC	Aamir Bohra
2019-08-05	soc/intel/cnl/graphics: Hook up libgfxinit	Nico Huber
2019-08-04	soc/intel/common/block/uart: Update the UART PCI device reference	Aamir Bohra
2019-08-02	soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabled	Aamir Bohra
2019-08-02	soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usage	Subrata Banik
2019-08-02	soc/intel/common/pch: Move thermal kconfig selection into common/pch	Subrata Banik
2019-08-01	soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registers	David Wu
2019-07-31	soc/intel/cannonlake: Enable FSP to use coreboot stack for cometlake	Aamir Bohra
2019-07-31	soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix	Sumeet Pawnikar
2019-07-30	soc/intel/cnl: Only print ME status one time	Tim Wawrzynczak
2019-07-30	soc/intel/cannonlake: Allow coreboot to handle required chipset lockdown	Subrata Banik
2019-07-30	soc/intel/cannonlake: Add new PCI IDs	Felix Singer
2019-07-30	soc/intel/{broad,cannon,sky}: Fix possible out-of-bounds reads	Jacob Garber
2019-07-29	soc/intel/cannonlake: Correct the data type of serial_io_dev	Aamir Bohra
2019-07-25	soc/intel: Guard remaining SA_DEV_ROOT definition	Kyösti Mälkki
2019-07-25	soc/intel/cannonlake: Split the "internal PME" wake-up into more detail	Paul Fagerburg
2019-07-21	soc/intel: Expand SA_DEV_ROOT for ramstage	Kyösti Mälkki
2019-07-21	soc/intel: Fix chip_info for PCH_DEV_PMC	Kyösti Mälkki
2019-07-19	soc/intel/common: Add SOC specific function to get XHCI USB info	Karthikeyan Ramasubramanian
2019-07-18	soc/intel: Use config_of()	Kyösti Mälkki
2019-07-18	soc/intel: Use config_of_path(SA_DEVFN_ROOT)	Kyösti Mälkki
2019-07-17	soc/intel/cannonlake: Add device Ids for new CFL SKUs support	Lean Sheng Tan
2019-07-17	soc/intel: Fix regression with hidden PCI devices	Kyösti Mälkki
2019-07-16	soc/intel/{cnl,icl}: Always use CAR NEM enhanced by default	Angel Pons
2019-07-15	intel/cannonlake: Fix indentation	Kyösti Mälkki
2019-07-13	soc/intel/cannonlake: Remove unused header files from southbridge.asl	Aamir Bohra
2019-07-13	cpu/x86: Move smm_lock() prototype	Kyösti Mälkki
2019-07-13	soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP	Nico Huber
2019-07-12	soc/intel/common: Add Coffee Lake H 6+2 Xeon graphics id	Nico Huber
2019-07-12	soc/intel/common: Add CM246 LPC device id	Nico Huber
2019-07-11	soc/intel/cannonlake: Add GPID and CGPM methods to GPIO ASL	Tim Wawrzynczak
2019-07-11	soc/intel/cannonlake: Make EC S0ix notification optional in LPIT	Tim Wawrzynczak
2019-07-11	soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer	Subrata Banik
2019-07-10	soc/intel: Remove invalid smm_relocate stubs	Kyösti Mälkki
2019-07-09	arch/x86: Flip HAVE_MONOTONIC_TIMER default	Kyösti Mälkki
2019-07-09	cpu/x86: Flip SMM_TSEG default	Kyösti Mälkki
2019-07-07	soc/intel/{cannonlake,icelake}: Do not define PCH_DEV_PMC in ramstage	Furquan Shaikh
2019-07-07	soc/intel/cannonlake, mb/google/sarien: Get rid of unused dev param	Furquan Shaikh
2019-07-07	soc/intel/cannonlake: Use SA_DEV_ROOT instead of PCH_DEV_PMC	Furquan Shaikh
2019-07-06	soc/intel/cannonlake: Fix outb order	Jeremy Soller
2019-07-06	soc/intel/cannonlake: Override PRERAM_CBMEM_CONSOLE_SIZE default value	Subrata Banik
2019-07-05	soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-H	Jeremy Soller
2019-07-04	soc/intel: Replace uses of dev_find_slot()	Kyösti Mälkki
2019-07-04	arch/x86: Adjust size of postcar stack	Kyösti Mälkki