coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-05-18	soc/intel: Fill DIMM serial number from SPD	Duncan Laurie
2019-05-15	soc/intel/cannonlake: Support different SPD read type for each slot	Philip Chen
2019-05-13	soc/intel/{cannonlake,icelake}: Drop unused cbmem.c file	Elyes HAOUAS
2019-05-11	soc/intel/cnl: Enable VT-d	John Zhao
2019-05-09	soc/intel/cannonlake: Fix pcie clock number	Lijian Zhao
2019-05-07	mb/google/sarien: Add SMBIOS type 9 fields	Lijian Zhao
2019-05-06	soc/intel/cannonlake/acpi: Add board level s0ix call back	Eric Lai
2019-05-06	soc/intel/cannonlake: Add GPIO dual-route support.	Tim Wawrzynczak
2019-05-01	mb/google/sarien: Disable S5 wake on LAN by default	Eric Lai
2019-04-30	vboot: refactor OPROM code	Joel Kitching
2019-04-29	soc/intel: Add GPI interrupt config register offset info	Karthikeyan Ramasubramanian
2019-04-29	soc/intel/cannonlake: Modify dq_map to provide for 6 entries	Paul Fagerburg
2019-04-26	soc/{amd,intel}/chip: Use local include for chip.h	Elyes HAOUAS
2019-04-25	3rdparty/fsp: Update submodule pointer to upstream master	Matt DeVillier
2019-04-23	soc/intel/cannonlake: add missing console.h include	Patrick Georgi
2019-04-23	soc/intel/cannonlake: Enable PlatformDebugConsent by Kconfig	Kane Chen
2019-04-23	soc/intel/cannonlake: Add null reference check for Cnvi and Xdci	Aamir Bohra
2019-04-23	src: include <assert.h> when appropriate	Elyes HAOUAS
2019-04-23	src: Add missing include 'console.h'	Elyes HAOUAS
2019-04-22	Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"	Lijian Zhao
2019-04-19	soc/intel/cannonlake: Add report for iGD 0x3ea1	Lijian Zhao
2019-04-18	soc/intel/cnl: Generate DMAR ACPI table	John Zhao
2019-04-16	soc/intel/cannonlake: Configure Vmx support using Kconfig	Ronak Kanabar
2019-04-16	soc/intel/cannonlake: Implement soc side VMX support	Ronak Kanabar
2019-04-16	soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML	Subrata Banik
2019-04-13	soc/intel/cpulib: Remove redundent enable/disable functions	Subrata Banik
2019-04-12	soc/intel/cannonlake: Select FSP_M_XIP	Furquan Shaikh
2019-04-12	soc/intel/cannonlake: Do not use XIP_ROM_SIZE	Furquan Shaikh
2019-04-11	soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups	Aamir Bohra
2019-04-08	Replace remaining IS_ENABLED(CONFIG_*) with CONFIG()	Nico Huber
2019-04-08	src/soc/intel/cannonlake: Remove ITSS IPC restore	Aamir Bohra
2019-04-06	src: Use include <delay.h> when appropriate	Elyes HAOUAS
2019-04-06	src: Use #include <timer.h> when appropriate	Elyes HAOUAS
2019-04-01	soc/intel/cannonlake: Add FSP UPD to unlock GPIO pads in devicetree	Krishna Prasad Bhat
2019-03-29	soc/intel/cannonlake: Ignore GBE LTR	Lijian Zhao
2019-03-28	soc/intel/cannonlake: Update CPU Ratio base on MSR	Lijian Zhao
2019-03-27	soc/intel/cannonlake: Configure voltage margining policies	Krzysztof Sywula
2019-03-25	soc/intel/cannonlake: Clear PMCON status bits	Krishna Prasad Bhat
2019-03-24	soc/intel/common: Remove common chip config use_fsp_mp_init	Subrata Banik
2019-03-22	soc/intel/cannonlake: Enable power button smi in pre-OS	Krzysztof Sywula
2019-03-21	soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports	Krishna Prasad Bhat
2019-03-20	src: Use 'include <string.h>' when appropriate	Elyes HAOUAS
2019-03-20	soc/intel/cannonlake: Fix return values for get_param_value	Furquan Shaikh
2019-03-18	soc/intel/cannonlake: Pass coreboot debug interface info to FSP	Maulik V Vaghela
2019-03-16	soc/intel/cannonlake: Add required FSP UPD changes for CML	Subrata Banik
2019-03-16	src: Drop unused '#include <halt.h>'	Elyes HAOUAS
2019-03-15	soc/intel/cannonlake: Fix GEN_PMCON bit checks	Furquan Shaikh
2019-03-13	soc/intel/cannonlake: Allow mainboard to override DRAM part number	Furquan Shaikh
2019-03-12	src: Drop unused 'include <arch/acpigen.h>'	Elyes HAOUAS
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner