summaryrefslogtreecommitdiff
path: root/src/soc/intel/cannonlake
AgeCommit message (Collapse)Author
2020-04-05fsp2_0: Gather Kconfig declarationsNico Huber
Move more Kconfig declarations to drivers/intel/fsp2_0/ and document them properly. This way, we don't have to repeat dependencies and have the prompts in a common place. We can also easily hide the prompt for the header path in case the FSP repository is used. SP platforms were skipped as their Kconfig is too weird but they shouldn't hold other platforms back. Change-Id: Iba5af49bcd15427e9eb9b111e6c4cc9bcb7adcae Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30intel/fsp2_0: Make FSP_USE_REPO a SoC opt-inJohanna Schander
For quite a bit now we are extending the FSP_USE_REPO option to be available for all Intel SoCs. This results in a list being not only hard to maintain but also prone to errors. To change that behaviour this commit introduces the HAVE_INTEL_FSP_REPO config option for SoCs that are supported from within 3rdparty/fsp. If a SoC selects HAVE_INTEL_FSP_REPO the config option FSP_USE_REPO is selected by default, but can be still deselected by the user in menuconfig. Change-Id: I68ae373ce591f06073064aa75aac32ceca8fa1cc Signed-off-by: Johanna Schander <coreboot@mimoja.de> Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37582 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25soc/intel/cometlake: Use IntelFSP repoFelix Singer
Make use of the publicly-available FSP binaries and headers for Comet Lake. Also, remove the Comet Lake header files from src/vendorcode, since they are no longer necessary. Change-Id: I392cc7ee3bf5aa21753efd6eab4abd643b65ff94 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39372 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23soc/intel/cfl/vr_config: Add 8-core desktop CPU supportPatrick Rudolph
Add 8-core desktop CPU support by adding the corresponding PCI IDs. Tested using "Intel Core(TM) i7-9700E". Change-Id: I7a2e2e5fd1796deff81b032450242fb58031526d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-17soc/intel/cannonlake: Set correct serirq modeJeremy Soller
Set FSP params PchSirqEnable/PchSirqMode based on board setting of serirq_mode. Matches implementation on Skylake. This is a no-change for existing boards since the default remains SERIRQ_QUIET mode. Tested on system76 galp3-c, out-of-tree WHL-U board Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nathaniel L Desimone <nathaniel.l.desimone@intel.com>
2020-03-12soc/intel/*/smihandler: Only compile in TCO SMI handler if neededPatrick Georgi
commit 7f9ceef disables TCO SMIs unless specifically enabled, so help the linker throw out the function that handles them in that case. Change-Id: Ia3c93b46e979fb8b99282875b188415f249d38dd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michael Niewöhner
2020-03-10soc/intel: fix eist enablingMatt Delco
There was a bug like this for skylake that seems to have been copied to other SoCs. Signed-off-by: Matt Delco <delco@chromium.org> Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-07intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registersMichael Niewöhner
Add registers that are relevant for the case intrusion detection functionality. Intel documents: 332691-003EN, 335193-006, 341081-001, ... Change-Id: If12d21e8e6721abb877cbbfbbba8f0127a86d96b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-07intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selectedMichael Niewöhner
Enable TCO SMIs in common code, if selected by Kconfig. This is needed for the follow-up commits regarding INTRUDER interrupt. Tested on X11SSM-F. Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-04soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZEArthur Heymans
The cache as ram code will use one form of a non-eviction mode. Change-Id: I418eb48434aa3da3bf5ca65315bb8c9077523966 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04src: capitalize 'PCIe'Elyes HAOUAS
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-02soc/intel/{common, skl, cnl, apl}: Move print_me_fw_version() to CSE libSridhar Siricilla
Move print_me_fw_version(), remove print_me_version/dump_me_version from cnl/skl/apl and make changes to call print_me_version() which is defined in the CSE lib. TEST=Verified on hatch, soraka and bobba. Change-Id: I7567fac100b14dc207b7fc6060e7a064fb05caf6 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-28soc/intel/cannonlake: Plumb TetonGlacierMode into dtEdward O'Callaghan
The following plumbs through the enabling of Intel's TetonGlacierMode allows for reconfiguring the PCIe lanes at runtime for hybrid drives to be accessable via devicetree. BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration on Puff. Change-Id: Id9a72161494db6a4da4abd3302b06df7c70634ab Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-26soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resumeSubrata Banik
This patch makes all legacy 8254 FSP UPDs (Enable8254ClockGating and Enable8254ClockGatingOnS3) depend on CONFIG_USE_LEGACY_8254_TIMER to avoid discrepancy between S0 and S3 resume flow. TEST=Able to boot to TianoCore without any hangs and errors, also verified S3 resume path doesn't clock gate 8254 timer using FSP-S UPD. Change-Id: Id6fe74a51537abbb9ff48db925e37a64e5b21f78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39110 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25soc/intel/common/block: Move cse common functions into block/cseSubrata Banik
This patch cleans soc/intel/{cnl, icl, tgl} by moving common soc code into common/block/cse. Supported SoC can select existing HECI_DISABLE_USING_SMM option to select common cse code block to make heci function disable using sideband interface during SMM mode at preboot envionment. BUG=b:78109109 TEST=Able to make HECI disable in SMM mode successfully without any hang or errors in CNL, ICL and TGL platform. Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26133 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25soc/intel/common/block: Move smihandler common functions into common codeSubrata Banik
This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc code into common/block/smihandler.c BUG=b:78109109 TEST=Build and boot KBL/CNL/APL/ICL/TGL platform. Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-25soc/intel/cannonlake: Add TDC config for CMLMarx Wang
Add Thermal Design Current (TDC) defaults for CML: 1. TdcEnable 2. TdcPowerLimit BUG=b:148912093 BRANCH=None TEST=build coreboot and Intel FSP with fw_debug enabled, flash image to the device, capture the log from the serial port during boot-up and check TdcEnable and TdcPowerLimit for each domain in captured log Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: Ie4b17e5b4ce41c1adb436ae5646f0d8578a440e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-24soc/intel/cnl: Rename hfsts into me_hfstsSridhar Siricilla
Remove me_hfs3 union from cnl/me.c since it's already defined in soc/me.h. Rename below union tags for consistency: hfsts2 -> me_hfsts2 hfsts3 -> me_hfsts3 hfsts4 -> me_hfsts4 hfsts5 -> me_hfsts5 hfsts6 -> me_hfsts6 TEST=Verified on hatch Change-Id: If81edbad0322425ee3e96c55a9c84a5087604308 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-17src/intel: Define HFSTS3 registerSridhar Siricilla
Changes: 1. Define HFSTS3 register across SoCs(apl/cnl/icl/tgl). 2. Define cse_is_hfs3_fw_sku_custom() which checks ME's Firmware SKU is Custom or not. TEST=Verified on hatch, soraka, bobba and iclrvp. Change-Id: I4188e58a4a08d87be2d84674e00ed1407fb8bf82 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-17soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774Wim Vervoorn
Make sure the Skylake comment refers to the correct BWG paragraph and update the text for all. BUG=N/A TEST=build Change-Id: Id383f200e079bdb91cea2240bd7a957d723a7b89 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-17soc/intel{cnl,icl,skl,tgl}/bootblock: Make sure DMI PCR 2770 is setWim Vervoorn
DMI PCR 2770 (LPC IO DECODE RANGES) should be identical to LPC PCI offset 0x80. This is specified in PCH BWG par 2.5.1.5. Add the support to make sure this PCR is always set correctly. BUG=N/A TEST=tested on facebook monolith. Change-Id: I33ff2b96dea78b5ff1c7c9416cf74f67d79f265d Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38746 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17vboot: remove VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT optionJoel Kitching
With CL:1940398, this option is no longer needed. Recovery requests are not cleared until kernel verification stage is reached. If the FSP triggers any reboots, recovery requests will be preserved. In particular: - Manual requests will be preserved via recovery switch state, whose behaviour is modified in CB:38779. - Other recovery requests will remain in nvdata across reboot. These functions now only work after verstage has run: int vboot_check_recovery_request(void) int vboot_recovery_mode_enabled(void) int vboot_developer_mode_enabled(void) BUG=b:124141368, b:35576380 TEST=make clean && make test-abuild BRANCH=none Change-Id: I52d17a3c6730be5c04c3c0ae020368d11db6ca3c Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38780 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09soc/intel/{cnl,icl,skl,tgl,common}: Make changes to ↵Sridhar Siricilla
send_heci_reset_req_message() Below changes have been implemented in send_heci_reset_req_message(): 1. Modify return values to align with other functions in the same file. 2. Add additional logging. 3. Replace macro definitions of reset types with ENUM. 4. Make changes to caller functions to sync with new return values. 5. Rename send_heci_reset_req_message() to cse_request_global_reset(). Test=Verified on hatch board. Change-Id: I979b169a5bb3a5d4028ef030bcef2b8eeffe86e3 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37584 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoCSridhar Siricilla
Below changes are implemented: 1. Move HFSTS1 register definition to SoC since HFSTS1 register definition is specific to a SoC. Moving structure back to SoC specific to avoid unnecessay SoC specific macros in the common code. 2. Define a set of APIs in common code since CSE operation modes and working states are same across SoCs. cse_is_hfs1_com_normal(void) cse_is_hfs1_com_secover_mei_msg(void) cse_is_hfs1_com_soft_temp_disable(void) cse_is_hfs1_cws_normal(void) 3. Modify existing code to use callbacks to get data of me_hfs1 structure. TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards. Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-04soc/intel: Add get_pmbaseEugene Myers
Originally a part of security/intel/stm. Add get_pmbase to the intel platform setup code. get_pmbase is used by the coreboot STM setup functions to ensure that the pmbase is accessable by the SMI handler during runtime. The pmbase has to be accounted for in the BIOS resource list so that the SMI handler is allowed this access. Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2 Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-04soc/intel/cannonlake: Allow Audio DSP OSC qualification for low power idleAamir Bohra
With Audio DSP OSC qualification disabled from S0ix criteria. S0ix is achieved before the DSP is suspended. When driver tries to suspend DSP its already turned off. BUG=b:139481313 Change-Id: I20b793b95483af03ce4ae068ac07864a9e90d39b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37604 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-04soc/intel: Remove duplicate CPUID entrySubrata Banik
This patch removes duplicate CPUID entry between KBL and CFL. CFL-D0 has KBL CPU + CNP PCH hence no need to redefine same KBL CPUID (0x806EA) for CFL-D0. TEST=CFL-D0 report platform serial msg shows "Cofeelake D0" with CPUID 0x806EA. Change-Id: I078dd7860891896b512967dc8dec5dd94d069193 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-01-18soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDsGaggery Tsai
This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for 10-Core ID. Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-18soc/intel/cannonlake: Add chip config for SATA strengthJamie Chen
Add config to chip.h for tuning SATA gen3 strength. BUG=b:147351936 BRANCH=none TEST=build successful in puff Change-Id: I4dcd23834fa3c01c1d88697a7bb8cf361709b62e Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38432 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-16soc/intel/{cnl,icl,skl, tgl}: Move SOC_INTEL_COMMON_BLOCK_THERMAL into SoC ↵Subrata Banik
specific Kconfig This patch moves common pch code SOC_INTEL_COMMON_BLOCK_THERMAL Kconfig selection into SoC specific Kconfig selection as PCH thermal device is not available with latest PCH (i.e. TGP and JSP). Also added TODO for TGL thermal configuration as applicable. TEST=Able to build and boot TGL RVP with this CL Change-Id: Ibce17cc9f38fb666011ccd8f97bee63033ff5302 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38444 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14soc/intel/cannonlake: Fix ASL compilation remarksSubrata Banik
This patch fixes below ASL compilation remarks 1. dsdt.asl 495: Method (_DSM, 4) Remark 2119 - ^ Control Method marked Serialized (Due to use of Switch operator) 2. dsdt.asl 721: Name(GPMB, Package(5) {0}) Remark 2063 - ^ Initializer list shorter than declared package length Change-Id: Iabd6c39025713dda7aa69cb479f003fbec8855b3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource properSubrata Banik
This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable. Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU. Unable to boot with dGPU on IA platform with below error: [ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR. Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2020-01-09sb/intel/common: Add smbus_set_slave_addr()Kyösti Mälkki
Change-Id: I7dddb61fab00e0f4f67d4eebee0cfe8dcd99f4ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38230 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpiSubrata Banik
This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to refer northbridge.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS. Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08soc/intel/cannonlake: Add VR config for CMLJamie Chen
Add VR config IccMax, DC and AC loadline defaults for CML. Add cpu_pl2_4_cfg to switch two kinds of VR design. BUG:b:145094963 BRANCH:none TEST:build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. All VR configs were set correctly. Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2020-01-08soc/intel/cannonlake: Add Comet Lake H SA 4+2 Device IDJamie Chen
This patch adds CML-H 4+2 SA DID into systemagent.c and report platform. According to doc #605546: CML-H (4+2) R1: 9B64h BUG:none BRANCH:none TEST:build no error Change-Id: I5bac6173a84a11abd2ce17f82854fbb14fb8558b Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2020-01-07soc/intel/{apl,cnl,icl,skl,tgl}: Clean up SA ASL codeSubrata Banik
List of changes in this patch 1. Remove unused variables 2. Make use of absolute path 3. Define macros and use inside SA ASL 4. Rearrange code in nothbridge.asl to move MCRS object under _CRS Change-Id: Id74269ec5a96b087562ccdf2141233db5585ae59 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2020-01-06soc/intel/cannonlake: Add VR config for CFL, CNL and WHLPatrick Rudolph
Add VR config IccMax, DC and AC loadline defaults and voltage regulator maximum for all CFL, CNL and WHL. This supports mainboards with replaceable CPUs and provides sane defaults for boards that are missing the devicetree overwrite. Remove the default IccMax to make use of the introduced lookup-table. Also change some hex values to decimal. I couldn't find CML datasheet, so those are left out for now. Used Doc #337344 and #338023 Section 7. Change-Id: I1d2e174157d468830cc0baf2a2d8295ef61a1a63 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37466 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADTMeera Ravindranath
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is set because PM timer emulation is enabled via MSR 121h so the timer will still work and can be used by things like Tianocore and Windows. Porting from 662b6cb3ed (soc/intel/skylake: Always add PM1_TMR block to FADT). Change-Id: Ie3d592623f3a84051477ffe83a0cf0daf30dd36f Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-26soc/intel/cannonlake: Move GPIO PM configuration to soc levelEric Lai
Enable GPIO clock gating when enter s0ix/Sx and save the PM bits. Restore the PM bits when exit s0ix/Sx. BUG=b:144002424 TEST=Check GPIO PM bits when enter/exit s0ix are expected Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-26soc/intel/cannonlake: Clean up report_cpu_info() functionUsha P
This patch makes below clean-up for report_cpu_info() function. 1. Remove unused variables. 3. Reuse fill_processor_name. TEST = Successfully able to boot hatch and verify the cpu_name "CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz" Change-Id: I41c76eb93f0c5229c4a49ab041339b6ad51ad24a Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-12-26soc/intel/cannonlake: Refactor pch_early_init() codeUsha P
This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBus init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=Able to build and boot hatch successfully. Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-12-19{drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoCWim Vervoorn
FSP logo handling used FspsConfig.LogoPtr and FspsConfig.LogoSize which are chipset specific. Create soc_load_logo() which will pass the logo pointer and size. This function will call fsp_load_logo which will load the logo. BUG=NA TEST= Build and verified logo is displayed on Facebook Monolith Change-Id: I30c7bdc0532ff8823e06f4136f210b542385d5ce Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37792 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src/soc/intel: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I71a5a6c3748d5a3910970bfb1ec3d7ecd3184cfd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33686 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src: Use '#include <smp/node.h>' when appropriateElyes HAOUAS
Change-Id: Icdd6b49751763ef0edd4c57e855cc1d042dc6d4d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-17soc/intel{cannonlake,icelake}/northbridge.asl: Correct flash rangeWim Vervoorn
The base address of the 16 MB flash range was reported as 0xFFF00000 this causes the range to extend above the 4GB boundary. Change the base to 0xFF000000 as is the case with e.g. Skylake. BUG=N/A TEST=build Change-Id: Ia8de01769ced00c5ae13f255760401933230b88c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-16src/soc/intel/cannonlake: Bump MAX_CPU from 8->12Edward O'Callaghan
This impacts boards: hatch (&variants) and drallion. Some variants like Puff can have up to 12 cores. coreboot should take the min() where MAX_CPU is the upper bound. Further to that, boards themseleves shouldn't be setting the MAX_CPUS, the chipset should be and so do that. BRANCH=none BUG=b:146255011 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I284d027886f662ebb8414ea92540916ed19bc797 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-163rdparty/fsp: Update to current master againNico Huber
We had to role the `fsp` submodule back for a minute due to a regression with the Coffee Lake binary. Intel silently mixed FSP 2.1 features into the Coffee Lake FSP which is supposed to be FSP 2.0. With the stack and heap usage partitioned for FSP using coreboot's stack (config FSP_USES_ CB_STACK), it works again. To make this even messier: We already selected this Kconfig option for Whiskey Lake, which is supposed to use the very same FSP binary. So with either submodule pointer, something was always broken :-/ Change-Id: Id2aa17aaa2c843dcc7e0fb28779d1e5948da83c9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mimoja <coreboot@mimoja.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 14:50:17 +0000