coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-02-26	soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO	Rizwan Qureshi
2019-02-26	soc/intel/common: Include cometlake PCH IDs	Ronak Kanabar
2019-02-24	soc/intel/common: Include cometlake SA IDs	Ronak Kanabar
2019-02-24	soc/intel/common: Include cometlake CPU IDs	Ronak Kanabar
2019-02-23	soc/intel/cannonlake: Make few more whitespace proper in MCH name	Subrata Banik
2019-02-22	soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from device...	Jeremy Soller
2019-02-22	soc/intel/cannonlake: Add ASL function for setting pad mode	Rizwan Qureshi
2019-02-22	soc/intel/cannonlake: Add whitespace proper in CPU/MCH/IGD name	Subrata Banik
2019-02-21	soc/intel/cannonlake: SoC specific microcode update check	Ronak Kanabar
2019-02-21	soc/intel/cannonlake: Add field to identify single channel memory	Shelley Chen
2019-02-21	src/soc/intel/cannonlake: Add PsysPmax setting	Gaggery Tsai
2019-02-20	src/soc/intel/cannonlake: Add _DSM methods for LPIT table	Lijian Zhao
2019-02-19	soc/intel/common: Add whiskeylake celeron v-0 support	Lijian Zhao
2019-02-18	soc/intel: Add mem_rank info in SMBIOS	Francois Toguo
2019-02-15	soc/intel/cannonlake: Define VR settings	Roy Mingi Park
2019-02-13	soc/intel/cannonlake: Configure serial debug uart	Ronak Kanabar
2019-02-13	soc/intel/cannonlake: Don't use CAR_GLOBAL	Arthur Heymans
2019-02-07	soc/intel/cannonlake: Configure GPIOs again after FSP-S is done	Furquan Shaikh
2019-02-07	soc/intel/cannonlake: Add Whiskeylake SoC kconfig	Subrata Banik
2019-02-04	soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT Kconfig	Subrata Banik
2019-01-31	soc/intel/cannonlake: Make correct C-state entries for S0ix and non-S0ix	Ronak Kanabar
2019-01-28	src/soc/intel/cnl/chip.h: Fix preprocessor condition	Angel Pons
2019-01-25	soc/intel/cannonlake: Export function to set After G3 state	Duncan Laurie
2019-01-25	soc/intel/cannonlake: Disable CpuRatio and SaGv in recovery	Duncan Laurie
2019-01-23	soc/intel/cannonlake: Replace device name B0D4 with TCPU	Sumeet Pawnikar
2019-01-17	soc/intel/cannonlake: drop extra newline	Patrick Georgi
2019-01-17	soc/intel/cannonlake: Change in SaGv options	Ronak Kanabar
2019-01-16	soc/intel/cannonlake: Fix afterg3 programming	Lijian Zhao
2019-01-16	soc/intel/cannonlake: Access conf pointer only if its not null	Pratik Prajapati
2019-01-16	soc/intel/cannonlake: Add processor power limits control support	Sumeet Pawnikar
2019-01-16	buildsystem: Promote rules.h to default include	Kyösti Mälkki
2019-01-14	soc/intel/cannonlake: Provide interface to update TCC offset	John Su
2019-01-12	soc/intel/cannonlake: Hook up Microcode	Lijian Zhao
2019-01-10	soc/intel/cannonlake: complete rename of TCO2_STS_SECOND_TO	Patrick Georgi
2019-01-10	soc/intel/common/block: Move tco common functions into block/smbus	Subrata Banik
2019-01-10	Untangle CBFS microcode updates	Nico Huber
2019-01-09	soc/intel: Clean mess around UART_DEBUG	Nico Huber
2019-01-09	soc/intel/cannonlake: Enable/Disable IPU based on devicetree switch	V Sowmya
2019-01-08	soc/intel/cannonlake: Add FSP UPD for minimum assertion width	Duncan Laurie
2019-01-08	soc/intel/cannonlake: Add chipset event logging	Duncan Laurie
2019-01-08	soc/intel/cannonlake: Fix chipset_power_state structure	Duncan Laurie
2019-01-07	soc/intel: Standardize names of common MSRs	Elyes HAOUAS
2019-01-06	soc/intel: Drop pmc_get_mainboard_power_failure_state_choice()	Nico Huber
2019-01-03	soc/intel/cannonlake: Add cannonlake ACPI GPIO op	Lijian Zhao
2019-01-01	soc/intel/cannonlake: Enable CNVi based on devicetree	Maulik V Vaghela
2018-12-19	soc/intel/cannonlake: SATA and DMI power optimize	Lijian Zhao
2018-12-19	soc/intel/cannonlake: Auto turn on HDA controller	Lijian Zhao
2018-12-19	soc/intel/cannonlake: Declare SATA Mode clear	Lijian Zhao
2018-12-19	soc/intel/cannonlake: Enable CPU flexible ratio	Lijian Zhao
2018-12-19	soc/intel/cannonlake: Amend comment typo	Lijian Zhao