coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-03-18	soc/intel/cannonlake: Pass coreboot debug interface info to FSP	Maulik V Vaghela
2019-03-16	soc/intel/cannonlake: Add required FSP UPD changes for CML	Subrata Banik
2019-03-16	src: Drop unused '#include <halt.h>'	Elyes HAOUAS
2019-03-15	soc/intel/cannonlake: Fix GEN_PMCON bit checks	Furquan Shaikh
2019-03-13	soc/intel/cannonlake: Allow mainboard to override DRAM part number	Furquan Shaikh
2019-03-12	src: Drop unused 'include <arch/acpigen.h>'	Elyes HAOUAS
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-07	soc/intel/cannonlake: Add support for logging wake source in SMM	V Sowmya
2019-03-07	soc/intel/cannonlake: Move power_state functions to pmutil.c	V Sowmya
2019-03-04	device/mmio.h: Add include file for MMIO ops	Kyösti Mälkki
2019-03-04	arch/io.h: Drop unnecessary include	Kyösti Mälkki
2019-03-04	soc/intel/cannonlake: Move common definitions to a header file	Rizwan Qureshi
2019-03-04	soc/intel/cnl/acpi: add ish ACPI device	Jett Rink
2019-03-04	soc/intel/cannonlake: Fix DSDT compile remarks	Lijian Zhao
2019-03-04	arch/x86/acpi: Remove obsolete acpi_gen_regaddr resv field	Elyes HAOUAS
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2019-02-28	soc/intel/cannonlake: Add CometLake SoC support	Subrata Banik
2019-02-28	soc/intel/cannonlake: Disable ACPI mode on BS_DEV_INIT exit	Furquan Shaikh
2019-02-28	soc/intel/cannonlake: Add PCH series check for CML LP PCH	Maulik V Vaghela
2019-02-28	soc/intel/cannonlake: Add Comet Lake U SA 2+2 Device ID	Subrata Banik
2019-02-27	soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#	Rizwan Qureshi
2019-02-27	soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffers	Rizwan Qureshi
2019-02-27	soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_init	Furquan Shaikh
2019-02-26	soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO	Rizwan Qureshi
2019-02-26	soc/intel/common: Include cometlake PCH IDs	Ronak Kanabar
2019-02-24	soc/intel/common: Include cometlake SA IDs	Ronak Kanabar
2019-02-24	soc/intel/common: Include cometlake CPU IDs	Ronak Kanabar
2019-02-23	soc/intel/cannonlake: Make few more whitespace proper in MCH name	Subrata Banik
2019-02-22	soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from device...	Jeremy Soller
2019-02-22	soc/intel/cannonlake: Add ASL function for setting pad mode	Rizwan Qureshi
2019-02-22	soc/intel/cannonlake: Add whitespace proper in CPU/MCH/IGD name	Subrata Banik
2019-02-21	soc/intel/cannonlake: SoC specific microcode update check	Ronak Kanabar
2019-02-21	soc/intel/cannonlake: Add field to identify single channel memory	Shelley Chen
2019-02-21	src/soc/intel/cannonlake: Add PsysPmax setting	Gaggery Tsai
2019-02-20	src/soc/intel/cannonlake: Add _DSM methods for LPIT table	Lijian Zhao
2019-02-19	soc/intel/common: Add whiskeylake celeron v-0 support	Lijian Zhao
2019-02-18	soc/intel: Add mem_rank info in SMBIOS	Francois Toguo
2019-02-15	soc/intel/cannonlake: Define VR settings	Roy Mingi Park
2019-02-13	soc/intel/cannonlake: Configure serial debug uart	Ronak Kanabar
2019-02-13	soc/intel/cannonlake: Don't use CAR_GLOBAL	Arthur Heymans
2019-02-07	soc/intel/cannonlake: Configure GPIOs again after FSP-S is done	Furquan Shaikh
2019-02-07	soc/intel/cannonlake: Add Whiskeylake SoC kconfig	Subrata Banik
2019-02-04	soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT Kconfig	Subrata Banik
2019-01-31	soc/intel/cannonlake: Make correct C-state entries for S0ix and non-S0ix	Ronak Kanabar
2019-01-28	src/soc/intel/cnl/chip.h: Fix preprocessor condition	Angel Pons
2019-01-25	soc/intel/cannonlake: Export function to set After G3 state	Duncan Laurie
2019-01-25	soc/intel/cannonlake: Disable CpuRatio and SaGv in recovery	Duncan Laurie
2019-01-23	soc/intel/cannonlake: Replace device name B0D4 with TCPU	Sumeet Pawnikar
2019-01-17	soc/intel/cannonlake: drop extra newline	Patrick Georgi
2019-01-17	soc/intel/cannonlake: Change in SaGv options	Ronak Kanabar