Age | Commit message (Expand) | Author |
2019-09-16 | src/soc/intel/{common,cnl,skl,icl}: Move global reset req function to common | Sridhar Siricilla |
2019-09-15 | src/soc: Remove unused include <device/pci_ops.h> | Elyes HAOUAS |
2019-09-13 | soc/intel/cannonlake: Allow coreboot to reserve stack for fsp | Bora Guvendik |
2019-09-12 | soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usage | Subrata Banik |
2019-09-12 | src/soc/intel/common/block/cse: Make hfsts1 common & add helper functions | Sridhar Siricilla |
2019-09-12 | soc/intel/cannonlake: Add config for sata devslp pad reset configuration | Aamir Bohra |
2019-09-12 | soc/intel/{cnl, icl}: Cache the TSEG region | Subrata Banik |
2019-09-11 | intel/fsp2_0: Add help text for FSP_TEMP_RAM_SIZE Kconfig | Subrata Banik |
2019-09-11 | soc/intel/common/block/cse: Move me_read_config32() to common code | Sridhar Siricilla |
2019-09-09 | soc/intel/cannonlake: Allow coreboot to handle SPI lockdown | Subrata Banik |
2019-09-09 | soc/intel/cannonlake: Add ability to disable Heci1 | Bora Guvendik |
2019-09-05 | soc/intel/cannonlake: memory spd data debug | Eric Lai |
2019-09-02 | security/intel: Add TXT infrastructure | Patrick Rudolph |
2019-08-28 | soc/intel: Move fill_postcar_frame to memmap.c | Kyösti Mälkki |
2019-08-28 | soc/intel/cnl: Add CML IGD IDs | Meera Ravindranath |
2019-08-27 | soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code | Subrata Banik |
2019-08-26 | intel/car: Use common TS_START_ROMSTAGE | Kyösti Mälkki |
2019-08-26 | lib/bootblock: Add simplified entry with basetime | Kyösti Mälkki |
2019-08-26 | soc/intel: Use common romstage code | Kyösti Mälkki |
2019-08-26 | soc/intel/cannonlake: Add config to disable display audio codec | Aamir Bohra |
2019-08-22 | arch/x86: Add <arch/romstage.h> | Kyösti Mälkki |
2019-08-20 | soc/intel/cnl: Add provision to configure SD controller write protect pin | Aamir Bohra |
2019-08-16 | soc/intel/cannonlake: Add 4E/4F to early io init | Christian Walter |
2019-08-16 | soc/intel/cannonlake: Add more PCI Ids for Coffeelake | Christian Walter |
2019-08-15 | intel/smm: Define struct ied_header just once | Kyösti Mälkki |
2019-08-15 | soc/intel: Rename some SMM support functions | Kyösti Mälkki |
2019-08-15 | intel/ice,sky,cannon: Drop unused EMRR and UNCORE_EMRR code | Kyösti Mälkki |
2019-08-15 | soc/intel: Drop spurious includes | Kyösti Mälkki |
2019-08-15 | mainboard/google: Fix indirect includes | Kyösti Mälkki |
2019-08-15 | cpu/x86/smm: Define single smm_subregion() | Kyösti Mälkki |
2019-08-13 | cpu/x86: Separate save_state struct headers | Kyösti Mälkki |
2019-08-11 | arch/x86: Flip option NO_CAR_GLOBAL_MIGRATION | Kyösti Mälkki |
2019-08-11 | arch/x86: Enable POSTCAR_CONSOLE by default | Kyösti Mälkki |
2019-08-09 | cpu/x86/smm: Drop SMI handler address from struct | Kyösti Mälkki |
2019-08-09 | soc/intel: Drop pmc_soc_restore_power_failure() | Nico Huber |
2019-08-09 | soc/intel/{cnl,icl}: Use new power-failure-state API | Nico Huber |
2019-08-08 | soc/intel: Fix SMRAM base MSR | Kyösti Mälkki |
2019-08-08 | arch/x86: Handle smm_subregion() failure | Kyösti Mälkki |
2019-08-08 | arch/x86: Change smm_subregion() prototype | Kyösti Mälkki |
2019-08-08 | lib/stage_cache: Refactor Kconfig options | Kyösti Mälkki |
2019-08-07 | cpu/x86/smm: Promote smm_subregion() | Kyösti Mälkki |
2019-08-07 | intel/icelake,skylake,cannonlake: Drop unused parameter | Kyösti Mälkki |
2019-08-05 | soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC | Aamir Bohra |
2019-08-05 | soc/intel/cnl/graphics: Hook up libgfxinit | Nico Huber |
2019-08-04 | soc/intel/common/block/uart: Update the UART PCI device reference | Aamir Bohra |
2019-08-02 | soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabled | Aamir Bohra |
2019-08-02 | soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usage | Subrata Banik |
2019-08-02 | soc/intel/common/pch: Move thermal kconfig selection into common/pch | Subrata Banik |
2019-08-01 | soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registers | David Wu |
2019-07-31 | soc/intel/cannonlake: Enable FSP to use coreboot stack for cometlake | Aamir Bohra |