coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-06-06	src: Remove unused 'include <cpu/x86/mtrr.h>'	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-05-01	src: Remove unused 'include <cpu/x86/cache.h>'	Elyes HAOUAS
2020-04-06	soc/intel/common: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-11-15	soc/intel/common: Make alignment proper for comments	Subrata Banik
2019-11-12	arch/x86/car.ld: Rename suffix _start/_end	Arthur Heymans
2019-09-11	arch/x86: Restrict use of _car_global[start\|end]	Kyösti Mälkki
2019-08-12	soc/intel/common: Fix typo mistake in cache_as_ram.S	Subrata Banik
2019-04-21	cpu/x86: Move checking for MTRR's as a proxy for proper CPU reset	Arthur Heymans
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-01-08	arch/x86: Link walkcbfs.S instead of including it	Arthur Heymans
2018-10-25	soc/intel: Consolidate FSP CAR setup and teardown code	Praveen hodagatta pranesh
2018-10-11	src: Move common IA-32 MSRs to <cpu/x86/msr.h>	Elyes HAOUAS
2018-06-04	src/soc: Get rid of whitespace before tab	Elyes HAOUAS
2018-04-25	soc/intel/common: disable paging if PAGING_IN_CACHE_AS_RAM enabled	Aaron Durbin
2018-02-20	src/soc: Fix various typos	Jonathan Neuschäfer
2017-10-16	intel/common: CAR setup CQOS	Naresh G Solanki
2017-06-29	arch/x86: update assembly to ensure 16-byte alignment into C	Aaron Durbin
2017-03-28	soc/intel/common/block: Add cache as ram init and teardown code	Subrata Banik