| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-05-22 | soc/intel/common: Add Intel PCIe common code | Aamir Bohra | |
| Add PCIe code support under soc/intel/common/block to initialize PCIe controller, allocate resources and configure L1 substate latency. Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> | |||
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index : coreboot | |
| Some coreboot project code with my work | vimacs |
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