coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-06-30	soc/intel/skylake: Generate ACPI RMRR table	Matt DeVillier
2018-04-24	compiler.h: add __weak macro	Aaron Durbin
2018-04-11	soc/intel/common: Configure all possible GFX DSM memory reserve range	Subrata Banik
2018-03-26	soc/intel: Add KBL-S MCH and some KBL PCH support	Gaggery Tsai
2018-02-20	src/soc: Fix various typos	Jonathan Neuschäfer
2018-02-07	soc/intel/skylake: Add Kabylake PCH H device ID's	V Sowmya
2017-12-13	soc/intel/common/block: Add option to have subsystem_id in common pci driver	Subrata Banik
2017-09-22	soc/intel/common: Add function to get soc reserved memory size	Subrata Banik
2017-09-14	intel/common/systemagent: Add API to get SOC specific PRMRR base and mask	Pratik Prajapati
2017-08-30	soc/intel/common: Add functions into common system agent library	Subrata Banik
2017-08-23	soc/intel/common: Early system agent library access in postcar stage	Subrata Banik
2017-08-23	soc/intel/common: Add functions into common system agent library	Subrata Banik
2017-08-04	soc/intel/common: Add Cannonlake pci ids for common	Lijian Zhao
2017-06-16	src/soc/intel: Don't allow user to select PCIe config mmio size	Arthur Heymans
2017-06-16	src/soc/intel/common: Don't allow user to change PCIe BAR	Arthur Heymans
2017-06-09	soc/intel/common/block: Add Intel common systemagent support	Subrata Banik
2017-03-28	soc/intel/common/block: Add Intel common systemagent support	Subrata Banik