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2016-12-02soc/intel/common: Add suppport for Extended VBTAbhay Kumar
With addition of new features in VBT its size got increased more than 6k and was unable to pass using mailbox 4 hence pass using mailbox 3 to kernel. BRANCH=none BUG=chrome-os-partner:60026 TEST=firmware screen and Chrome OS screen should come up. Change-Id: I359cf9bc402881161c9623cada689496716e04a5 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/17585 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01lib/nhlt: add support for setting the oem_revisionAaron Durbin
In the ACPI header there's an OEM revision field that was previously just being implicitly set to 0. Allow for a board to provide a non-zero value for this field. Change-Id: Icd40c1c162c2645b3990a6f3361c592706251f82 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17650 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-30soc/intel/common: Add save/restore for variable MRC dataAndrey Petrov
Piggy-back on existing MRC cache infrastructure to store variable MRC data. Only one set of data can be valid at given point of time. Currently this magically happens because region alignment is forced to 0x1000 and region itself is of the same size. This needs to be somehow programmatically enforced. Change-Id: I8a660d356ca760b8ff9907396fb9b34cb16cf1db Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17320 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22soc/intel: Use correct terminology for SPI flash operationsFurquan Shaikh
FPR is an attribute of the SPI flash component and not of the SPI bus itself. Rename functions, file names and Kconfig option to make sure this is conveyed correctly. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: I9f06f1a8ee28b8c56db64ddd6a19dd9179c54f50 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17560 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-19soc/intel/common/lpss_i2c: correct bus speed errorAaron Durbin
The wrong value was used for reporting an error when a requested bus speed was made that isn't supported. Use the requested value. Change-Id: I6c92ede3d95590d95a42b40422bab88ea9ae72a1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17474 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-19soc/intel/common/lpss_i2c: fix NULL dereference in error pathAaron Durbin
If the SoC clock speed is not supported there is supposed to be an error printed. However, the value printed was wrong which was dereferencing a NULL struct. Fix that. Change-Id: I5021ad8c1581d1935b39875ffa3aa00b594c537a Found-by: Coverity Scan #1365977 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17468 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-12soc/intel/common/lpss_i2c: configure buses by rise/fall timesAaron Durbin
The default register count calculations are leading to higher frequencies than expected. Provide an alternative method for calculating the register counts by utilizing the rise and fall times of the bus. If the rise time is supplied the rise/fall time values are used, but the register overrides take precedence over the rise/fall time calculation. This allows platforms to choose whichever method works the best. BUG=chrome-os-partner:58889 Change-Id: I7747613ce51d8151848acd916c09ae97bfc4b86a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17350 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-11soc/intel/common/lpss_i2c: simplify API and use common config structureAaron Durbin
The apollolake and skylake had duplicate stanzas of code for initializing the i2c buses. Additionally, they also had very similar structures for providing settings for the i2c speed control. Introduce a new struct lpss_i2c_bus_config and utilize it in both apollolake and skylake thereby removing the need for SoC-specific structres. The new structure is used for initializing a bus fully as the lpss i2c API is simplified in that lpss_i2c_init() is only required to be called. The struct lpss_i2c_bus_config structure is passed in for both initializing and filling in the SSDT information. The formerly exposed functions are made static to reduce the external API exposure. BUG=chrome-os-partner:58889 Change-Id: Ib4fa8a7a4de052da75c778a7658741a5a8e0e6b9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17348 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-10mrc: Add support for separate training cache in recovery modeFurquan Shaikh
1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or RECOVERY_MRC_CACHE based on the boot mode. - If normal mode boot, use RW_MRC_CACHE, if available. - If recovery mode boot: - Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is requested explicity with retrain memory request. - Use RECOVERY_MRC_CACHE otherwise. 2. Protect RW and RECOVERY mrc caches in recovery and non-recovery boot modes. Check if both are present under one unified region and protect that region as a whole. Else try protecting individual regions. 3. Update training data in appropriate cache: - Use RW_MRC_CACHE if normal mode. - Use RECOVERY_MRC_CACHE if present in recovery mode. Else use RW_MRC_CACHE. 4. Add proper debug logs to indicate which training data cache is used at any point. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified that correct cache is used in both normal and recovery mode on reef. Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17242 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07lpss_i2c: Increase transaction timeoutDuncan Laurie
When doing long transcations on an I2C bus at standard speed we saw that long transactions could go over the 4ms limit while waiting for it to complete on the bus. Increase this so we can use standard speed for testing and debug in firmware. (as there is no way to force standard speed in the kernel) BUG=chrome-os-partner:58666 TEST=boot eve board with cr50 TPM and I2C bus at 100khz Change-Id: I2987ae6a5aa024b373eb088767194c70b0918b6f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17213 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-06soc/intel/common: log event when MRC cache is updatedAaron Durbin
Log when the MRC cache is attempted to be updated with status of success or failure. Just one slot is supported currently which is deemed 'normal'. This is because there are more slots anticipated in the future. BUG=chrome-os-partner:59395 Change-Id: I0f81458325697aff9924cc359a4173e0d35da5da Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17231 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-10-29soc/intel/common: Add reset.c to postcarFurquan Shaikh
ramstage_cache_invalid which was added in I83fe76957c061f20e9afb308e55923806fda4f93 (review.coreboot.org/#/c/17112) requires hard_reset to be defined in postcar stage. BUG=None BRANCH=None TEST=Compiles successfully for reef. Change-Id: I283277c373259e0e2dfe72e3c889ceea012544f2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17182 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26soc/intel/common: Enable support to write protect SPI flash rangeFurquan Shaikh
Write-protect SPI flash range provided by caller by using a free Flash Protected Range (FPR) register. This expects SoC to define a callback for providing information about the first FPR register address and maximum number of FPRs supported. BUG=chrome-os-partner:58896 Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17115 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-14lpss_i2c: Add Kconfig option to enable debugDuncan Laurie
It is very useful to have the ability to see I2C transactions performed by the host firmware. This patch adds a simple Kconfig option that will enable debug output. Change-Id: I55f1ff273290e2f4fbfaea56091b2df3fc49fe61 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16590 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-14lpss_i2c: Change handling of controller enable/disableDuncan Laurie
This change modifies the lpss_i2c driver to behave more like the Linux kernel driver. In particular the controller is only enabled when processing a transaction, and is disabled after. This means that errors in one transaction will not affect later transactions. Also when disabling the controller the code is supposed to wait on the enable bit in the "enable status" register and not in the enable control register. In order to get access to this register the reg map was expanded to include all registers. This was tested with the cr50 TPM driver to ensure that if a transaction does fail that it can be successfully retried instead of the bus being unusable. Change-Id: I43a546d54996ba0f08550a801927b8f7a6690cda Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16589 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04lpss_i2c: Increase default timeout to 4msDuncan Laurie
Increase the default timeout in the LPSS I2C driver to 4ms from 2ms. During testing with some slower devices I found that the existing timeout could be too short leading to transaction failures. Change-Id: Ied86c7a0aa26d55b31f447c5938803c194d0045e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16392 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-31src/soc: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16324 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-25intel/common: Clear wake status bits before sleepShaunak Saha
Call power management utility function clear_wake_sts from southbridge_smi_sleep before going to sleep. This is needed to clear the wake status bits in ACPI registers GPE0. BUG=chrome-os-partner:55583 BRANCH=None TEST=Verified that system goes to sleep on lidclose and powerd_dbus_suspend command issued from built-in keyboard. Change-Id: I204a59f8a19137d6a192ea2d89939eefcd5d41ce Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16299 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11soc/intel/common: Add support for serial console based ACPI debugSubrata Banik
This patch enables serial debug functionality for ASL code based on UART type(legacy/LPSS). From Skylake onwards all Intel platform uses LPSS based UART for serial console hence provide option to redirect ASL log over LPSS UART. Example: Name (OBJ, 0x12) APRT (OBJ) APRT ("CORE BOOT") Output: 0x12 CORE BOOT BUG=none BRANCH=none TEST=Built and boot kunimitsu to ensure to be able to get ASL console log. Change-Id: I18c65654b8eb1ac27af1f283d413376fd79d47db Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/16070 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-08soc/intel/common: fix gsmi handlerAaron Durbin
The gsmi_exec() expects the parameter to be a pointer to the 32-bit register storage of the SMI save state. The previous code was passing a pointer with the value obtained from the saved-state -- not a pointer to the storage of the register value. This bug causes gsmi to not log events because it's interrogating the parameter buffer itself as if it were a pointer. BUG=chrome-os-partner:55932 Change-Id: I37981424f1414edad1456b31cad1b99020d57db6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16087 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-01soc/intel/common: Fix build error in reset.cLee Leahy
Fix build error caused by macro substitution in the function definition when the Kconfig value HAVE_HARD_RESET is not selected. src/soc/intel/common/reset.c:36:21: error: macro "hard_reset" passed 1 arguments, but takes just 0 void hard_reset(void) ^ src/soc/intel/common/reset.c:37:1: error: expected '=', ',', ';', 'asm' or '__attribute__' before '{' token { ^ make: *** [build/bootblock/soc/intel/common/reset.o] Error 1 TEST=Build and run on Galileo Gen2 Change-Id: I793570e62a0e46cca86cc540c243e363896ceac7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15988 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-01soc/intel/common: Enable MTRR display during bootblock & postcarLee Leahy
Update Makefile.inc to allow MTRR display during bootblock and postcar. TEST=Build and run on Galileo Gen2 Change-Id: If12896df46b9edfc9fff3fab3a12d2dae23517a3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15990 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31src/soc: Capitalize CPU, ACPI, RAM and ROMElyes HAOUAS
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-29soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resumeAbhay Kumar
Do not pass VBT table to fsp in normal mode and S3 resume so that PEIM GFX will not get initialized. Change-Id: Iab7be3cceb0f80ae0273940b36fdd9c41bdb121e Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/14575 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-28intel/common: Add ASL code for DPTFShaunak Saha
This patch adds the common ASL code for Intel platforms. This is the basic ASL needed to add support for DPTF controlled devices. We are moving these commmon ASL files to src/soc/intel/common/acpi as these are same codes used in all Intel platforms and hence no need to duplicate. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: I01078382a9008263c6ad99f6bf07558885af6a63 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15093 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28intel/common/opregion.c: only write 16 bytes to 16 byte fieldMartin Roth
Including the terminating null, 17 characters were being written to the field, overwriting the a byte of the size field. Fortunately, the size was updated soon after this. Fixes coverity warning 1229570 - Destination buffer too small. Change-Id: I39285a9283dd9a17d638afe5b2755c7e420d7698 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15889 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-28soc/intel/skylake: Add C entry bootblock supportSubrata Banik
List of activity performing in this patch - early PCH programming - early SA programming - early CPU programming - mainborad early gpio programming for UART and SPI - car setup - move chipset programming from verstage to post console BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and booted kunimitsu till POST code 0x34 Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15785 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and developer mode check functions to vboot. Thus, get rid of the BOOTMODE_STRAPS option which controlled these functions under src/lib. BUG=chrome-os-partner:55639 Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27soc/intel/common: Store MRC data in next available slot in the cacheFurquan Shaikh
Currently, coreboot performs an erase of the entire MRC cache region on flash if there is a version mismatch for the MRC data. Instead of doing that, store the new MRC data in the next available slot, if there is enough space available in the cache region. BUG=chrome-os-partner:55699 Change-Id: Ib24a94f0a47c79941ed9f60095360ae3aad5540b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15915 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27cpu/x86: Support CPUs without rdmsr/wrmsr instructionsLee Leahy
Quark does not support the rdmsr and wrmsr instructions. In this case use a SOC specific routine to support the setting of the MTRRs. Migrate the code from FSP 1.1 to be x86 CPU common. Since all rdmsr/wrmsr accesses are being converted, fix the build failure for quark in lib/reg_script.c. Move the soc_msr_x routines and their depencies from romstage/mtrr.c to reg_access.c. TEST=Build and run on Galileo Gen2 Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15839 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19soc/intel/common: Add reset_prepare() for common resetAndrey Petrov
Some Intel SoC may need preparation before reset can be properly handled. Add callback that chip/soc code can implement. BUG=chrome-os-partner:55055 Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15720 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15soc/intel/common: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I40560b2a65a0cff6808ccdec80e0339786bf8908 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15668 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-01skylake: Generate ACPI timing values for I2C devicesDuncan Laurie
Have the Skylake SOC generate ACPI timing values for the enabled I2C controllers instead of passing it in the DSDT with static timings. The timing values are generated from the controller clock speed and are more accurate than the hardcoded values that were in the ASL which were originally copied from Broadwell where the controller is running at a different clock speed... Additionally it is now possible for a board to override the values using devicetree.cb. If zero is passed in for SCL HCNT or LCNT then the kernel will generate its own timing using the same forumla, but if the SDA hold time value is zero the kernel will NOT generate a correct value and the SDA hold time may be incorrect. This was tested on the Chell platform to ensure all the I2C devices on the board are still operational with these new timing values. Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01soc/intel/common: use nvs.h include for nhlt codeAaron Durbin
The nvs.h header is the one which defines global_nvs_t proper. Don't rely on an indirect inclusion. Change-Id: I89d6a73f65e408c73f068b4a35b5efd361a6e5d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15503 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-29soc/intel/{common,skylake}: provide common NHLT SoC supportAaron Durbin
The nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides() functions should be able to be leveraged on all Intel SoCs which support NHLT. Therefore provide that functionality and make skylake use it. Change-Id: Ib5535cc874f2680ec22554cecaf97b09753cacd0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15490 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-22soc/intel/common/acpi: Add _PTS, _WAK methodsHannah Williams
Change-Id: I72f894fd14bf0e333d9fda970397a3c82de598c3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15121 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21lpss_i2c: Set SDA hold and support custom speed configDuncan Laurie
This I2C controller has separate registers for different speeds to set specific timing for SCL high and low times, and then a single register to configure the SDA hold time. For the most part these values can be generated based on the freq of the controller clock, which is SOC-specific. The existing driver was generating SCL HCNT/LCNT values, but not the SDA hold time so that is added. Additionally a board may need custom values as the exact timing can depend on trace lengths and the number of devices on the I2C bus. This is a two-part customizaton, the first is to set the values for desired speed for use within firmware, and the second is to provide those values in ACPI for the OS driver to consume. And finally, recent upstream changes to the designware i2c driver in the Linux kernel now support passing custom timing values for high speed and fast-plus speed, so these are now supported as well. Since these custom speed configs will come from devicetree a macro is added to simplify the description: register "i2c[4].speed_config" = "{ LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30), LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30), LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30), LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30), }" Which will result in the following speed config in \_SB.PCI0.I2C4: Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) Name (FPCN, Package () { 52, 120, 30 }) Name (HSCN, Package () { 38, 90, 30 }) Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15163 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-20soc/intel/common: Add _OSC methodHannah Williams
Not masking any bits in Operating System Capabilities, which means we support all the capabilities that OS passed in Arg3 Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15021 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-12soc/intel/common: don't infinitely recurse in busmaster_disable_on_bus()Aaron Durbin
If a bridge has the primary bus equal to the secondary bus the busmaster_disable_on_bus() will infinitely call itself. Avoid the inifinite recursion by checking current bus number against the secondary bus number. BUG=chrome-os-partner:54262 TEST=Ran on reef. Able to actually get the chipset to assert SLP_Sx signals which means no more infinite recursion. Change-Id: I52b21fbba24e6a652ea8f9f87f5f49f60109c8f2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15157 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-09soc/intel/common: Add LPSS I2C driverDuncan Laurie
Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys DesignWare I2C block and have a similar configuration of that block. This driver is ported from the Chromium depthcharge project where it was ported from U-Boot originally, though it looks very different now. From depthcharge it has been modified to fit into the coreboot I2C driver model with platform_i2c_transfer() and use coreboot semantics throughout including the stopwatch API for timeouts. In order for this shared driver to work the SOC must: 1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock speed that the I2C controller core is running at. 2) Define the lpss_i2c_base_address() function to return the base address for the specified bus. This could be either done by looking up the PCI device or a static table if the controllers are not PCI devices and just have a static base address. The driver is usable in verstage/romstage/ramstage, though it does require early initialization of the controller to set a temporary base address if it is used outside of ramstage. This has been tested on Broadwell and Skylake SOCs in both pre-RAM and ramstage environments by reading and writing both single bytes across multiple segments as well as large blocks of data at once and with different configured bus speeds. While it does need specific configuration for each SOC this driver should be able to work on all Intel SOCs currently in src/soc/intel. Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15101 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08soc/intel/common: Add common code for acpi c/p/t-state entriesHannah Williams
Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-25soc/intel/common: Add common smihandler codeHannah Williams
Provide default handler for some SMI events. Provide the framework for extracting data from SMM Save State area for processors with SMM revision 30100 and 30101. The SOC specific code should initialize southbridge_smi with event handlers. For SMM Save state handling, SOC code should implement get_smm_save_state_ops which initializes the SOC specific ops for SMM Save State handling. Change-Id: I0aefb6dbb2b1cac5961f9e43f4752b5929235df3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18soc/intel/common: Add IGD OpRegion supportAndrey Petrov
Add helper function that fills OpRegion structure based on VBT file content and some reasonable defaults. Change-Id: I9aa8862878cc016a9a684c844ceab390734f3e84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18soc/intel/common: Add utility to load VBT fileAndrey Petrov
Change-Id: I8d3d47ca2fc1fc4c10e61c04b941b6378b9c0f80 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14815 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-12soc/intel/common/mrc_cache: Don't assume FMAP is tied to CHROMEOSAlexandru Gagniuc
The old code only checked for an RW_MRC_CACHE region when CONFIG_CHROMEOS was selected. This assumption is not necessarily true, as one can have FMAP without a CHROMEOS build. As a result, always search FMAP first before falling back on CBFS for locating the MRC cache region. The old logic where CHROMEOS builds would fail when RW_MRC_CACHE was not found is preserved, such that behavior does not change. Change-Id: I3596ef3235eff661af055968ea641f3e9671cdcd Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14757 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-10intel/common/mma: override SAGV to fixed high for MMA testsPratik Prajapati
Set SAGV to 2 (Fixed High) so that MMA test would stress memory at high freq point. MMA tests does not support stressing memory at both high and low points. BRANCH=glados BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu and ran MMA tests. Change-Id: I0b2f6cf9955076f6146b957c4d40fe24e6c3f0e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b16b756d9a74c9111c78fce848b059daee65669 Original-Change-Id: I4c4a59407844e1986fa2cf3a0035aff1d8529cf9 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339002 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-(cherry picked from commit c43d9880fe4efd1e1bb853d35140424fb7dd7e99) Original-Reviewed-on: https://chromium-review.googlesource.com/338847 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/14697 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10util/mma: changing BOOT_STUB to COREBOOT region and few more thingsPratik Prajapati
(1) Added following new function. cbfs_locate_file_in_region - to locate (and mmap) a file in a flash region This function is used to look for MMA blobs in "COREBOOT" cbfs region (2) mma_setup_test.sh would write to "COREBOOT" region. (3) changes in mma_automated_test.sh. Few MMA tests need system to be COLD rebooted before test can start. mma_automated_test.sh would do COLD reboot after each test, and so i would sync the filesystem before doing COLD reboot. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB4). Able to locate MMA files in CBFS Not tested on Glados. Change-Id: I8338a46d8591d16183e51917782f052fa78c4167 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1e418dfffd8a7fe590f9db771d2f0b01a44afbb4 Original-Change-Id: I402f84f5c46720710704dfd32b9319c73c412e47 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331682 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/14125 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-04soc/intel/common/mrc_cache: Honor MRC data as a constant pointerAlexandru Gagniuc
The MRC cache API has absolutely no reason to modify the data it is asked to stash. Reflect that by taking all "data" parameters as const void *. Change-Id: I7a14ffd7d5726aa9aa5db81df82c06e7f87b9d9f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14250 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-11 05:06:03 +0000