| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-12-14 | soc/intel/elkhartlake: Update HECI Control Status Register settings | Tan, Lean Sheng |
| 2020-09-08 | soc/intel/elkhartlake: Do initial SoC commit till ramstage | Tan, Lean Sheng |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |