coreboot - Some coreboot project code with my work

Age	Commit message (Collapse)	Author
2019-02-11	soc/intel/fsp_broadwell_de: Move FSP_DEBUG_LEVEL option here	Nico Huber
	It is not mentioned in the FSP spec and doesn't seem to be implemented for any other FSP than the Broadwell-DE one. Change-Id: I87c758204f1aabf13f47de19fd87c6e1ed67258e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-14	intel/fsp1_0: Add option to select FSP debug level	Patrick Rudolph
	Useful for debugging FSP. Change-Id: I06e837cf1b051c55a531c3361e94fa1449bc8526 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-01-14	soc/intel/fsp_broadwell_de: Fix uart	Patrick Rudolph
	* Disable FSP serial output if not CONSOLE_SERIAL Tested on wedge100s. Change-Id: Idd825d2d6eb423452d3e81265860205980f6aa5b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-22	intel: Use CF9 reset (part 1)	Patrick Rudolph
	Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-05	fsp_broadwell_de: Add option to enable EHCI controllers	David Hendricks
	Change-Id: I74ee9448923015ac5ec3eec770669f3491a375ba Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/26042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16	intel/fsp_broadwell_de: Set FSP serial speed to match coreboot's	David Hendricks
	This makes FSP use the same baud rate as coreboot so that the user can more easily change it without having to modify the FSP binary. Change-Id: I0084aa9a0394ad7eabdd88809b66fc21a25ba316 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/25666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-04-20	intel/fsp_broadwell_de: fix SPD CBFS file type	Stef van Os
	File type for SPD in this soc is defined as CBFS_TYPE_RAW in Makefile, but CBFS_TYPE_SPD in code. Causes DDR SPD not to be loaded on memory down. Tested on Prodrive Technologies Broadwell-D 1548 module: http://prodrive-technologies.com/amc-ix5-intel-broadwell-de-platform/ Change-Id: I44525b4742b3f93d33f0c5bd9ed642c6fb06f23f Signed-off-by: Stef van Os <stef.van.os@prodrive-technologies.com> Reviewed-on: https://review.coreboot.org/14415 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: York Yang <york.yang@intel.com>
2016-04-14	soc/intel: Add Broadwell-DE SoC support	York Yang
	Initial files to support Broadwell-DE SoC. This is FSP 1.0 based project and is based on Broadwell-DE Gold release. Change has been verified on Intel Camelback Mountain CRB. Change-Id: I20ce8ee8dd1113a7a20a96910292697421f1ca57 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: https://review.coreboot.org/14014 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Martin Roth <martinroth@google.com>