coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-20	icelake: remove unused processor power limits configuration	Sumeet R Pawnikar
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	soc/intel/icelake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-04	src: capitalize 'PCIe'	Elyes HAOUAS
2020-03-01	soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig	Subrata Banik
2019-12-12	soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h	Furquan Shaikh
2019-11-04	soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig	Michael Niewöhner
2019-09-29	soc/intel: Rename <intelblocks/chip.h>	Kyösti Mälkki
2019-07-11	soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer	Subrata Banik
2019-06-09	soc/intel/icelake: Pass FSP-M/S UPD as per ICL requirement	Aamir Bohra
2019-05-20	soc/intel/icelake: Make use of gpio_pm_configure()	Subrata Banik
2018-12-10	mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters	Aamir Bohra
2018-11-22	soc/intel/icelake: Create macros for FSP consumption	Subrata Banik
2018-11-17	soc/intel/icelake: Make static IRQ mapping for PIC mode	Subrata Banik
2018-11-09	mb/intel/icelake_rvp: Move CNVi ASL entry from static DSDT to dynamic SSDT ge...	Subrata Banik
2018-10-26	soc/intel/icelake: Do initial SoC commit	Aamir Bohra