| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-11-05 | soc/intel/icelake: Add PID based on Icelake EDS | Aamir Bohra |
| 2018-11-02 | soc/intel/icelake: Allow coreboot to reserve stack for fsp | Aamir Bohra |
| 2018-11-01 | src: Add missing include <stdint.h> | Elyes HAOUAS |
| 2018-10-31 | soc/intel/icelake: Open ports 0x60,0x64 for keyboard controller | Shelley Chen |
| 2018-10-30 | src: Add missing include <stdint.h> | Elyes HAOUAS |
| 2018-10-27 | soc/intel/*: Make FSP header path user configurable | Patrick Georgi |
| 2018-10-26 | soc/intel/icelake: Do initial SoC commit | Aamir Bohra |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |