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coreboot
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broadwell_refcode
e6230
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Some coreboot project code with my work
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chip.h
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2020-10-26
mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
Michael Niewöhner
2020-10-12
soc/intel/jasperlake: Correct SaGv mapping
Aamir Bohra
2020-10-08
soc/intel/jasperlake: Add VR Configuration settings
Meera Ravindranath
2020-09-22
soc/intel/jasperlake: Enable processor thermal control using PCI_DEVFN
Sumeet R Pawnikar
2020-09-14
soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.h
Subrata Banik
2020-08-17
soc/intel/jasperlake: Add FSP UPDs for minimum assertion widths
V Sowmya
2020-07-23
soc/intel/jasperlake: Add the SkipCpuReplacementCheck configuration
V Sowmya
2020-05-18
jasperlake: update processor power limits configuration
Sumeet R Pawnikar
2020-05-12
soc/intel/jasperlake: Add SATA related UPDs configuration
Ronak Kanabar
2020-05-11
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-05-01
soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understa...
Subrata Banik
2020-05-01
soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree
Meera Ravindranath
2020-04-06
soc/intel/jasperlake: Use SPDX for GPL-2.0-only files
Angel Pons
2020-03-28
soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake
Aamir Bohra
2020-03-28
soc/intel/jasperlake: Add Jasper Lake SoC support
Aamir Bohra