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2018-11-23soc/intel/common: Bring DISPLAY_MTRRS into the lightNico Huber
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the "Debug" menu. It turned out, though, that the code looks rather generic. No need to hide it in soc/intel/. To not bloat src/Kconfig up any further, start a new `Kconfig.debug` hierarchy just for debug options. If somebody wants to review the code if it's 100% generic, we could even get rid of HAVE_DISPLAY_MTRRS. Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29684 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-15oc/intel/quark/Kconfig: Remove unused MMCOMF_SUPPORT_DEFAULTElyes HAOUAS
Change-Id: I24596b7b4f3e7caef7f42e4317a786caa42c5c2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-22intel: Use CF9 reset (part 2)Patrick Rudolph
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also implement board_reset() as a "full reset" (aka. cold reset) as that is what was used here for hard_reset(). Drop soc_reset_prepare() thereby, as it was only used for APL. Also, move the global-reset logic. We leave some comments to remind us that a system_reset() should be enough, where a full_reset() is called now (to retain current behaviour) and looks suspicious. Note, as no global_reset() is implemented for Denverton-NS, we halt there now instead of issuing a non-global reset. This seems safer; a non-global reset might result in a reset loop. Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-21soc/intel/quark/uart.c: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ia50aa96901b979b947fd4d269b077814c06f60c6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28677 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-09mainboard: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage. Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26984 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04soc/{amd,intel}: Use postcar_frame_add_romcache()Nico Huber
Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-31soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)Nico Huber
Boards could choose a high ROM_SIZE that would result in an MTRR config that conflicts with other resources. Thus, always use the filtered CACHE_ROM_SIZE. Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26575 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-28soc/intel/quark: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I102c9b9b1066064589149388d5ebbcd6d0d81fa7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-22bootblock: Allow more timestamps in bootblock_main_with_timestamp()Julius Werner
This patch adds more parameters to bootblock_main_with_timestamp() to give callers the opportunity to add additional timestamps that were recorded in the platform-specific initialization phase. Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
pci_bus_default_ops() is the default anyway. Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-30drivers/spi: support cmd opcode deduction for spi_crop_chunk()Aaron Durbin
spi_crop_chunk() currently supports deducting the command length when determining maximum payload size in a transaction. Add support for deducting just the opcode part of the command by replacing deduct_cmd_len field to generic flags field. The two enums supported drive the logic within spi_crop_chunk(): SPI_CNTRLR_DEDUCT_CMD_LEN SPI_CNTRLR_DEDUCT_OPCODE_LEN All existing users of deduct_cmd_len were converted to using the flags field. BUG=b:65485690 Change-Id: I771fba684f0ed76ffdc8573aa10f775070edc691 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23491 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-03soc/intel/quark/spi: Correct conversion specifierPaul Menzel
Use the correct conversion specifier for `size_t` to fix the error below. ``` from src/soc/intel/quark/spi.c:18: src/soc/intel/quark/spi.c: In function 'xfer': src/soc/intel/quark/spi.c:107:20: error: format '%ld' expects argument \ of type 'long int', but argument 3 has type 'unsigned int' \ [-Werror=format=] printk(BIOS_ERR, "bytesin > %ld\n", sizeof(ctrlr->data)); ^ ``` Found-by: gcc (Debian 7.2.0-8) 7.2.0 Change-Id: I3974d116e85715086a2bd5533a80a20c4cc43303 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/22130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-18include/device: Split i2c.h into threeNico Huber
Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14i2c: Move to Linux like `struct i2c_msg`Nico Huber
Our current struct for I2C segments `i2c_seg` was close to being compa- tible to the Linux version `i2c_msg`, close to being compatible to SMBus and close to being readable (e.g. what was `chip` supposed to mean?) but turned out to be hard to fix. Instead of extending it in a backwards compatible way (and not touching current controller drivers), replace it with a Linux source compatible `struct i2c_msg` and patch all the drivers and users with Coccinelle. The new `struct i2c_msg` should ease porting drivers from Linux and help to write SMBus compatible controller drivers. Beside integer type changes, the field `read` is replaced with a generic field `flags` and `chip` is renamed to `slave`. Patched with Coccinelle using the clumsy spatch below and some manual changes: * Nested struct initializers and one field access skipped by Coccinelle. * Removed assumption in the code that I2C_M_RD is 1. * In `i2c.h`, changed all occurences of `chip` to `slave`. @@ @@ -struct i2c_seg +struct i2c_msg @@ identifier msg; expression e; @@ ( struct i2c_msg msg = { - .read = 0, + .flags = 0, }; | struct i2c_msg msg = { - .read = 1, + .flags = I2C_M_RD, }; | struct i2c_msg msg = { - .chip = e, + .slave = e, }; ) @@ struct i2c_msg msg; statement S1, S2; @@ ( -if (msg.read) +if (msg.flags & I2C_M_RD) S1 else S2 | -if (msg.read) +if (msg.flags & I2C_M_RD) S1 ) @@ struct i2c_msg *msg; statement S1, S2; @@ ( -if (msg->read) +if (msg->flags & I2C_M_RD) S1 else S2 | -if (msg->read) +if (msg->flags & I2C_M_RD) S1 ) @@ struct i2c_msg msg; expression e; @@ ( -msg.read = 0; +msg.flags = 0; | -msg.read = 1; +msg.flags = I2C_M_RD; | -msg.read = e; +msg.flags = e ? I2C_M_RD : 0; | -!!(msg.read) +(msg.flags & I2C_M_RD) | -(msg.read) +(msg.flags & I2C_M_RD) ) @@ struct i2c_msg *msg; expression e; @@ ( -msg->read = 0; +msg->flags = 0; | -msg->read = 1; +msg->flags = I2C_M_RD; | -msg->read = e; +msg->flags = e ? I2C_M_RD : 0; | -!!(msg->read) +(msg->flags & I2C_M_RD) | -(msg->read) +(msg->flags & I2C_M_RD) ) @@ struct i2c_msg msg; @@ -msg.chip +msg.slave @@ struct i2c_msg *msg; expression e; @@ -msg[e].chip +msg[e].slave @ slave disable ptr_to_array @ struct i2c_msg *msg; @@ -msg->chip +msg->slave Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-03soc/intel/quark: Add I2C debuggingLee Leahy
Add I2C debugging support: * Add I2C_DEBUG Kconfig value to enable debugging * Display I2C segments before the transfer * Display errors that occur during the transfer * Display the number of bytes transferred for successful transfers TEST=Build and run on Galileo Gen2 Change-Id: Ia17be8b4213b13fd6c6a367d081414d0f21fbb0f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-07-02soc/intel/quark/spi.c: Explain a read in order to flush buffersMartin Kepplinger
In order for this (seemingly unnecessary) status assignment to stay, let's explain it in a comment. Change-Id: I0a364539c37005cfd637b75c8cc23b84e274294d Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/20411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-27soc/intel/quark: We're not Broadwell anymoreStefan Reinauer
... even though the author of the code probably wished he was working on a (much faster) broadwell system instead. Let's fix the header guard to reflect the right SOC. Noteworthy: clang detected that this was wrong. Change-Id: I74c217c0471800f40c31a9ac38ba5396f82cd724 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-20soc/intel/quark: Add legacy SPI flash controller driverLee Leahy
Add SPI driver code for the legacy SPI flash controller. Enable erase and write support allowing coreboot to save non-volatile data into the SPI flash. TEST=Build and run on Galileo Gen2. Change-Id: I8f38c955d7c42a1e58728c728d0cecc36556de5c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-06fsp1_1: Verify FSP_IMAGE_ID/_REV against headersNico Huber
FSP_IMAGE_ID and FSP_IMAGE_REV are defined in `FspUpdVpd.h`. Check against these to avoid mismatching definitions in coreboot and the FSP blob. Change-Id: Ic86229e7f0c2d0525b8a79add292c6c81a349aa6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-05-12commonlib: Move drivers/storage into commonlib/storageLee Leahy
Move drivers/storage into commonlib/storage to enable access by libpayload and indirectly by payloads. * Remove SD/MMC specific include files from include/device * Remove files from drivers/storage * Add SD/MMC specific include files to commonlib/include * Add files to commonlib/storage * Fix header file references * Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver * Add Kconfig source for commonlib/storage * Rename *DEVICE* to *COMMONLIB* * Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE* TEST=Build and run on Galileo Gen2 Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-05-08soc/intel/quark: Add SD/MMC test supportLee Leahy
The SD/MMC test support consists of: * Add Kconfig value to enable the SD/MMC test support. * Add Kconfig value to enable the logging support. * Add SD/MMC controller init code and read block 0 from each partition. * Add logging code to snapshot the transactions with the SD/MMC device. * Add eMMC driver for ramstage to call test code. * Add romstage code to call test code. * Add bootblock code to call test code. TEST=Build and run on Galileo Gen2 Change-Id: I72785f0dcd466c05c1385cef166731219b583551 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/19211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-19soc/intel/quark: Move include of reg_access.hLee Leahy
Move include of reg_access.h from pci_devs.h to reg_access.c. TEST=Build and run on Galileo Gen2 Change-Id: I0d2de96f51c56001cdd06c7974cbc649fde1e89c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19355 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15soc/intel/quark: Read the rmu.bin file from read-only regionLee Leahy
Always read the rmu.bin file from the read-only section of the SPI flash. Without this change vboot attempts to read this file from the A or B section of the flash. TEST=Build and run on Galileo Gen2 Change-Id: Ied8eaa2cd37645bf401aa957936943946bfd6182 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18803 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14soc/intel/quark: Pass S3 wake status to fsp_silicon_initLee Leahy
Fix build error with FSP 1.1. Pass the S3 wake status to fsp_silicon_init. TEST=Build and run on Galileo Gen2 Change-Id: I78150f737321db5b1b4d63b411fa6432ac30d080 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18805 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14soc/intel/quark: Add ESRAM display to FSP 1.1Lee Leahy
Add ESRAM display to FSP 1.1 TEST=Build and run on Galileo Gen2 Change-Id: Ia47b0bdba65606a7f0695332d298fc1e910b0e2f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18804 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14soc/intel/quark: Return NULL for top_of_memoryLee Leahy
Return NULL for top_of_memory when the register has not been set. TEST=Build and run on Galileo Gen2 Change-Id: If79cac68c2a64aa9bf3be72d3cfc4c73fceef12b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18802 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-13soc/intel/quark: Add the verstage filesLee Leahy
Add the files to support verstage for vboot. TEST=Build and run on Galileo Gen2 Change-Id: Icf87075012c08cf581c17d579e0763888c707265 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18040 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07soc/intel/quark: Fix errors detected by checkpatchLee Leahy
Fix the errors detected by checkpatch and update the copyright dates. TEST=Build and run on Galileo Gen2 Change-Id: Idad062eaeca20519394c2cd24d803c546d8e0ae0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18591 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07soc/intel/quark: Fix I2C driverLee Leahy
Fix the following issues: * A raw read is described by a single read segment, don't assert. * Support reads longer than the FIFO size. * Support writes longer than the FIFO size. * Use the 400 KHz clock by default. * Remove the error displays since vboot device polling generates errors. TEST=Build and run on Galileo Gen2 Change-Id: I421ebb23989aa283b5182dcae4f8099c9ec16eee Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18029 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-16intel: Fix copy/paste error in license textMarshall Dawson
Change all instances of "wacbmem_entryanty" to "warranty". Change-Id: I113333a85d40a820bd8745efe917181ded2b98bf Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18136 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-04soc/intel/quark: Add monotonic timer supportLee Leahy
Add the Kconfig value HAVE_MONOTONIC_TIMER and the routine to read the TSC for the monotonic timer. Simplify the routine to get the TSC frequency. TEST=Build and run on Galileo Gen2 Change-Id: I806fb864b01e39277bf2d6276254b0543930c2f6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18002 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03soc/intel/quark: Add early debugging codeLee Leahy
Add Kconfig values and early debugging code to better segment and debug the early code in bootblock by using the SD LED as an indicator. Update the help text for the debug Kconfig values to point to the various failure locations. TEST=Build and run on Galileo Gen2 Change-Id: I1cd62eba3e9547cb1dd7f547aaec5d4827e14633 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/17985 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03soc/intel/quark: Fix serial port configurationLee Leahy
Fix serial port configuration broken by how PCI configuration space was referenced introduced by change 3d15e10a (MMCONF_SUPPORT: Flip default to enabled). TEST=Build and run on Galileo Gen2 Change-Id: I2ab52cf598795e94f1f16977f8d12b7fdd95e146 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/17984 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-01romstage_handoff: add helper to determine resume statusAaron Durbin
Instead of having callers query the romstage handoff resume status by inspecting the object themselves add romstage_handoff_is_resume() so that the same information can be queried easily. Change-Id: I40f3769b7646bf296ee4bc323a9ab1d5e5691e21 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17647 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-30driver/intel/fsp2_0: Add version parameter to FSP platform callbackAndrey Petrov
Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-21fsp2_0: implement stage cache for silicon initBrandon Breitenstein
Stage cache will save ~20ms on S3 resume for apollolake platforms. Implementing the cache in ramstage to save silicon init and reload it on resume. This patch adds passing S3 status to silicon init in order to verify that the wake is from S3 and not for some other reason. This patch also includes changes needed for quark and skylake platforms that require fsp 2.0. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for reef and tested boot and S3 resume path saving 20ms Change-Id: I99dc93c1d7a7d5cf8d8de1aa253a326ec67f05f6 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/17460 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-30soc/intel/quark: Fix FSP 2.0 buildLee Leahy
Fix the build issues with FSP 2.0: * Remove struct from the various data structures. * Properly display the serial port UPDs. * Change chipset_handle_reset parameter type BRANCH=none BUG=None TEST=Build FSP 2.0 (SEC/PEI core with all FSP debug off) and run on Galileo Gen2 Change-Id: Icae578855006f18e7e5aa18d2fd196d300d0c658 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30soc/intel/quark: Support multiple version of FSPLee Leahy
Add support for multiple versions of FSP. BRANCH=none BUG=None TEST=Build FSP 1.1 (SEC/PEI core, with all FSP debug off) and run on Galileo Gen2 Change-Id: Ie7e7f0f883c4d3bfcb18fa25571e505cdde00b2d Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16807 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30mainboard/intel/quark: Add FSP selection valuesLee Leahy
Add Kconfig values to select the FSP setup: * FSP version: 1.1 or 2.0 * Implementation: Subroutine or SEC/PEI core based * Build type: DEBUG or RELEASE * Enable all debugging for FSP * Remove USE_FSP1_1 and USE_FSP2_0 Look for include files in vendorcode/intel/fsp/fsp???/quark BRANCH=none BUG=None TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2 Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16806 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31src/soc: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16324 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-15intel/quark: Fix assert checkFurquan Shaikh
Having an assignment in assert does not make sense. This seems like it was intended to check if chip is always same as segments->chip. Change-Id: I297d9e76a0404a1f510d43f8b9c39e96b557689f Reported-by: Coverity ID 1357439 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16219 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-08-10soc/intel/quark: Switch to using serial routines for FSPLee Leahy
Switch from passing FSP the serial port address to passing FSP the serial port output routine. This enables coreboot to use any UART in the system and also log the FSP output. TEST=Build and run on Galileo Gen2 Change-Id: I67d820ea0360a3188480455dd2595be7f2debd5c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16105 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 16:20:30 +0000