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2019-07-03soc/intel/skylake: Add Kabylake-R microcode update filesArthur Heymans
This also corrects some CPU naming in comments. Change-Id: I8b9fc3ba0d6dc6e0001b40518aae2d26c1184dc8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34000 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-01Use 3rdparty/intel-microcodeArthur Heymans
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel. This allows for some finegrained control where family+model span multiple targets. Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products. The following MCU are get a new revision: old: sig 0x000306c3, pf_mask 0x32, 2018-04-02, rev 0x0025, size 23552 sig 0x00040651, pf_mask 0x72, 2018-04-02, rev 0x0024, size 22528 sig 0x000206a7, pf_mask 0x12, 2018-04-10, rev 0x002e, size 12288 sig 0x000306a9, pf_mask 0x12, 2018-04-10, rev 0x0020, size 13312 sig 0x000706a1, pf_mask 0x01, 2018-05-22, rev 0x0028, size 73728 sig 0x000506c9, pf_mask 0x03, 2018-05-11, rev 0x0032, size 16384 sig 0x000506ca, pf_mask 0x03, 2018-05-11, rev 0x000c, size 14336 sig 0x000806e9, pf_mask 0xc0, 2018-03-24, rev 0x008e, size 98304 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000906ea, pf_mask 0x22, 2018-05-02, rev 0x0096, size 97280 sig 0x000906eb, pf_mask 0x02, 2018-03-24, rev 0x008e, size 98304 sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432 sig 0x000506e3, pf_mask 0x36, 2018-04-17, rev 0x00c6, size 99328 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000406e3, pf_mask 0xc0, 2018-04-17, rev 0x00c6, size 99328 new: sig 0x000306c3, pf_mask 0x32, 2019-02-26, rev 0x0027, size 23552 sig 0x00040651, pf_mask 0x72, 2019-02-26, rev 0x0025, size 21504 sig 0x000206a7, pf_mask 0x12, 2019-02-17, rev 0x002f, size 12288 sig 0x000306a9, pf_mask 0x12, 2019-02-13, rev 0x0021, size 14336 sig 0x000706a1, pf_mask 0x01, 2019-01-02, rev 0x002e, size 73728 sig 0x000506c9, pf_mask 0x03, 2019-01-15, rev 0x0038, size 17408 sig 0x000506ca, pf_mask 0x03, 2019-03-01, rev 0x0016, size 15360 sig 0x000806e9, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906ea, pf_mask 0x22, 2019-04-01, rev 0x00b4, size 98304 sig 0x000906eb, pf_mask 0x02, 2019-04-01, rev 0x00b4, size 99328 sig 0x00050665, pf_mask 0x10, 2019-03-23, rev 0xe00000d, size 19456 sig 0x000506e3, pf_mask 0x36, 2019-04-01, rev 0x00cc, size 100352 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000406e3, pf_mask 0xc0, 2019-04-01, rev 0x00cc, size 100352 Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-21soc/intel/skylake: Clean up KconfigArthur Heymans
This does the following: - select MAINBOARD_USES_FSP2_0 on Kabylake (does not support FSP1.1) - Remove stale Kconfig option on intel/saddlebrook - select SOC_INTEL_KABYLAKE on intel/kblrvp Change-Id: I64f48eeb00150aea039d533b0ac471fdd8483b90 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-21soc/intel/skylake: Remove ROMCCFLAGSArthur Heymans
This is never used. Change-Id: I414acc38f72e206eb48cfd98214985c320862c91 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-18soc/intel/skylake: Select microcode updates depending on discrete PCHArthur Heymans
Change-Id: I05e97484605306afc70c726187bda8091216c9cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-07intel/fsp1_1: Drop remnants of `pei_data`Nico Huber
`pei_data` was a struct with blob parameters from pre-FSP times. Somehow, it sneaked into upstream FSP1.1 support (probably because early board ports were written for a different blob). When added upstream, its usage was already perverted. It was declared at SoC level but mostly used to pass mainboard data from mainboard code to itself and FSP data from FSP code to itself. Now that no board/ SoC code uses it anymore, we can finally drop it. Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-09soc/intel: Clean mess around UART_DEBUGNico Huber
Everything is wrong here, the Kconfig symbols are only the tip of the iceberg. Based on Kconfig prompts the SoC code performed pad configu- rations! I don't see why the person who configures coreboot should have the board schematics at hand. As a mitigation, we remove the prompts for UART_DEBUG, which is renamed to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say what it's about), and for UART_FOR_CONSOLE in case the former is selec- ted. Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-11-07soc/intel/skylake: Add FSP CAR support for kabylakePraveen hodagatta pranesh
Kabylake RVP11 uses FSPT to support Intel security features like bootguard verify boot and measured boot. This patch add FSP CAR support for kabylake by programming tempraminit parameters in fspcar.c and also add FSP_T_XIP default if FSP_CAR is selected in order to relocate FSPT binary while adding it in CBFS so that it can be executed in place. BUG=None TEST=Build and Boot to UEFI payload on kabylake RVP11 board and verified for successful FSP CAR setup. Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52 Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-12drivers/intel/fsp2_0: Hook up IntelFSP repoPatrick Georgi
With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using Intel's FSP repo (that we mirror) to build a complete BIOS ifd region with a simple coreboot build, automatically drawing in headers and binaries. This commit covers Apollolake, Coffeelake, Skylake, and Kabylake. Skylake is using Kabylake's FSP since its own is FSP 1.1 and Kabylake's also supports Skylake. Another candidate (given 3rdparty/fsp's content) is Denverton NS, but it requires changes to coreboot's FSP bindings to become compatible. Cannonlake, Whiskeylake require an FSP release. Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28593 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21soc/intel/skylake: Include some microcode blobsArthur Heymans
This included the microcode for some CPUID's found in soc/intel/skylake/bootblock/report_platform.c (others are likely pre-release SKU's) The amount of FIT entries needed is currently 7 so setting CPU_INTEL_NUM_FIT_ENTRIES is set to a safe 10 will be able to fit them all. Change-Id: I3ba504a07b2697fe55ff8f28a934f761ae05a4ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-20soc/intel/skylake: add CPPC supportMatt Delco
ACPI 5.0 defines a method _CPC for "Continuous Performance Control" (CPPC). Linux has a driver that enables features like speed shift without consulting ACPI. Other OSes instead rely on this information and need a _CPC present. Prior to this change performance in Win10 never exceeds 80% and MSR 0x770 is 0, while with this change (and enabling eist) higher speeds can be achieved and the MSR value is now 1. Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-10drivers/i2c: Add i2c TPM support for different stagesPhilipp Deppenwiese
Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-06-28soc/intel/common/block: Move p2sb common functions into block/p2sbSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/p2sb. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22soc/intel/skylake: Make use of common SMM code for SKLSubrata Banik
This patch ensures skylake soc is using common SMM code from intel common block. TEST=Build and boot soraka/eve Change-Id: I8163dc7e18bb417e8c18a12628988959c128b3df Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/22826 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-08soc/intel/skylake: Clean up bootblock/report_platform.cSubrata Banik
This patch ensures that all required information for pch/mch/igd deviceid and revision available in single stage and make use of local references. TEST=Build and boot soraka/eve Change-Id: I6f7f219536831210750a486ee3b3308d6f285451 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22756 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07soc/intel/skylake: Clean up UART codeAamir Bohra
Clean up and move UART related code under a single uart.c file. Change-Id: I7ed03fc5fe79e38350d7edc70ad55d54db780fed Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-07soc/intel/skylake: Make use of Intel common Graphics blockSubrata Banik
TEST=Build and boot soraka/eve. Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-02soc/intel/common/block: Add Intel common PMC controller support for KBL, APLSubrata Banik
SoC needs to select specific macros to compile commom PMC code. TEST=Build and boot KBL (soraka/eve), APL (reef) Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-30soc/intel/skylake: Set low maximum temperature threshold for Thermal DeviceSubrata Banik
PMC logic shuts down the thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in S0ix is enabled. BUG=b:69110373 BRANCH=none TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)] value is 0xFA. Change-Id: I94d09a28bf1ea07a53cfa04c54752358bafca610 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28soc/intel/skylake: Make use of Intel common DSP blockSubrata Banik
TEST=Build and boot soraka/eve. Change-Id: I8be2a90dc4e4c5eb196af57045d2a46b7f0c9722 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11soc/intel/skylake: Make use of Intel SPI common blockSubrata Banik
TEST=Build and boot soraka/eve Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I10de3ff75a3b063c4c46471e380bbbe2630c35f3 Reviewed-on: https://review.coreboot.org/22361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19soc/intel/skylake: Support logging wake source in SMMFurquan Shaikh
This change adds support for logging wake source information in gsmi callbacks. With this change, all the elog logging infrastructure can be used for S0ix as well as S3 on skylake. BUG=b:67874513 Change-Id: Ie1f81e956fe0bbe2e5e4c706f27997b7bd30d5e0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16console/flashconsole: Enable support for postcarYouness Alaoui
If FSP 2.0 is used, then postcar stage is used and the flashconsole as well as spi drivers needed to be added. Change-Id: I46d720a9d1fe18a95c9407d08dae1eb70ae6720e Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/21959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/skylake: Enable common LPC IPRavi Sarawadi
Enable Skylake to use the new common LPC code. This will help to reduce code duplication and streamline code bring up. Change-Id: I042e459fb7c07f024a7f6a5fe7da13eb5f0dd688 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Move LPC lock down config after resource allocationSubrata Banik
This patch to ensures that coreboot is performing LPC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence lpc register lock down has been moved right after pci resource allocation is done, so that lpc registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure LPC register 0xDC bit 1 and 7 is set. Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-10soc/intel/skylake: Enable UART debug controller on S3 resumeFurquan Shaikh
1. Add a new variable to GNVS to store information during S3 suspend whether UART debug port controller is enabled. 2. On resume, read stored GNVS variable to decide if UART debug port controller needs to be initialized. 3. Provide helpers functions required by intel/common UART driver for enabling controller on S3 resume. BUG=b:64030366 TEST=Verified behavior with different combinations: 1. Serial console enabled in coreboot: No change in behavior. 2. Serial console enabled only in kernel: coreboot initializes debug controller on S3 resume. 3. Serial console not enabled in coreboot and kernel: coreboot skips initialization of debug controller on S3 resume. Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20886 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-24soc/intel/skylake: Use common opregion implementationPatrick Rudolph
Enable SOC_INTEL_COMMON_GFX_OPREGION for all FSP versions. Allows to get rid of opregion.c, as it's no longer needed. Change-Id: I39190488e12917a09dbf7ee3947a33940ebc290b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-07-10sgx: Move SGX code to intel/common/blockPratik Prajapati
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX controls building. The SGX feature is still enabled from devicetree.cb. As of now this SGX init supports only KBL (SKL not tested). Support of SGX for new SOCs would be added incrementally in this common code base. Change-Id: I0fbba364b7342e686a2287ea1a910ef9a4eed595 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/20173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/intel/skylake: Use CPU common library codeBarnali Sarkar
This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19566 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05soc/intel/skylake: Use Intel timer common codeAamir Bohra
Use timer code from soc/intel/common. This code removes monotonic timer refrence w.r.t MSR 24Mhz counter(0x637) and use tsc timer. Change-Id: I7fad620b11c9e5db128f646639c79ea58a0a574f Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-22soc/intel/skylake: Use Intel SATA common codeAamir Bohra
Use SATA common code from soc/intel/common/block/sata and clean up code. Change-Id: Ib5d65f1afda6b2f8098f1c006623a48cf2690593 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-22soc/intel/skylake: Use Intel PCIe common codeAamir Bohra
Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-18intel/common/block/i2c: Add common block for I2C and use the same in SoCsRizwan Qureshi
In the intel/common/block * Move I2C common code from intel/common to intel/common/block. * Split the code into common, early init and post mem init stages and put it in lpss_i2c.c, i2c_early.c and i2c.c respectively. * Declare functions for getting platform specific i2c bus config and mapping bus to devfn and vice versa, that have to be implemented by SoC. In skylake/apollolake * Stop using code from soc/intel/common/lpss_i2c.c. * Remove early i2c initialization code from bootblock. * Refactor i2c.c file to implement SoC specific methods required by the I2C IP block. Change-Id: I4d91a04c22e181e3a995112cce6d5f0324130b81 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/19468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-09soc/intel/skylake: Use intel/common/block/smbus codeAamir Bohra
Change-Id: I2ca32ab594552424e4f1358302641f159a3d7e62 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-02soc/intel/skylake: Clean up code by using common FAST_SPI moduleBarnali Sarkar
This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19055 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-25soc/intel/skylake: use postcar stage for fsp 2.0Aaron Durbin
Utilize the postcar stage for tearing down CAR and initializing the MTRRs once ram is up. This flow is consistent with apollolake and allows CAR_GLOBAL variables to be directly accessed and no need for migrating CAR_GLOBAL variables as romstage doesn't run with and without CAR being available. Change-Id: I76de447710ae1d405886eb9420dc4064aa26eccc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19335 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-10soc/intel/skylake: Use common PCR moduleSubrata Banik
This patch use common PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pcr_ids.h Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-06soc/intel/skylake: Add support for GSPI controllerFurquan Shaikh
Sky Lake PCH contains two GSPI controllers. Using the common GSPI controller driver implementation for Intel PCH, add support for GSPI controller buses on Sky Lake/Kaby Lake. BUG=b:35583330 Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19099 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05soc/intel/skylake: Add tsc_freq.c to verstageFurquan Shaikh
This is required to provide tsc freq required by timer library. BUG=b:35583330 TEST=Verified that delay(5) in verstage adds a delay of 5 seconds. Change-Id: I03edebe394522516b46125fae1a17e9a06fd5f45 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19094 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-28soc/intel/skylake: Clean up code by using common System Agent moduleSubrata Banik
This patch currently contains the SA initialization required for bootblock phase - 1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code. 2. Perform PCIEXBAR programming based on soc configurable PCIEX_LENGTH_xxxMB 3. Use common systemagent header file. Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18566 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28soc/intel/common/block: Add cache as ram init and teardown codeSubrata Banik
Create sample model for common car init and teardown programming. TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED and CAR_NEM configs till post code 0x2a. Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18381 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-23soc/intel/skylake: Add SGX initializationRobbie Zhang
This patch implements SGX initialization steps in coreboot per Intel SGX BWG rev 2.0.8 for Kaby Lake SoC. If enabled on a Kabylake device, SoC capability and PRM (processor reserved memory) of desired size (needs to be configured through PrmrrSize) are provisioned for later software stack to use SGX (i.e., run SGX enclaves). One issue is still puzzling and needs to be addressed: by calling configure_sgx() in cpu_core_init() which is the per-thread function, SGX is always failing for thread 0 but is successful for other 3 threads. I had to call configure_sgx() again from soc_init_cpus() which is the BSP-only function to make it enable on the BSP. Another pending work is the implementation for the Owner Epoch update which shall be added later. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve, verified SGX activation is successful on all threads. Change-Id: I8b64284875eae061fa8e7a01204d48d320a285a9 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18445 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06soc/intel/skylake: Use intel/common/xhci driverSubrata Banik
Change-Id: I7bd83d293fcc1848f6f64526d8f38d010c1f69a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18223 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22soc/intel/skylake: Include I2C code in romstageDuncan Laurie
The lpss_i2c driver is enabled in romstage, so the SOC needs to export the pre-ram compatible I2C controller info, which for skylake is in the bootblock/i2c.c file. This was not causing a compiler error in normal use, but when adding I2C debug code in romstage it failed to compile. With this added, I can now do I2C transactions in romstage. Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-23soc/intel/skylake: Use the new SPI driver interfaceFurquan Shaikh
1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCh=None TEST=Compiles successfully for chell and eve. Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-23soc/intel/skylake: Define early smbus functionsNaresh G Solanki
Define early smbus functions that can be used by mainboard to fetch spd. Change-Id: Id170b2b8e6fb3ebb147f37bf433a27d1162dc11c Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17433 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-07soc/intel/skylake: Fix SATA booting to OS issueSubrata Banik
SATA device remains unrecognized if connected at Port 2. Port control and Status register (PCS) is by default set by hardware to the disabled state as a result of an initial power on reset. OS read PCS register during boot causes disabling of SATA ports and can't detect any devices. BRANCH=none BUG=chrome-os-partner:59335 TEST=Build and boot SKL from SATA device connected at Port 2. Change-Id: I4866ca44567f5024edaca2d48098af5b4c67a7ac Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-28soc/intel/skylake: put back uart_debug.c into verstageAaron Durbin
uart_debug.c was accidentally dropped in verstage in 64ce1d122c0464a4ef138fb7452a91b408b1a7c2 (https://review.coreboot.org/17136). Fix that. Change-Id: If37a028550d419bada80d157c4de02fd82d26c89 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17175 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-10-27skylake: Support for early I2C TPM driverDuncan Laurie
Add the SOC definition for acpi_get_gpe() so it can be used by the I2C TPM driver. Also add the I2C support code to verstage so it can get used by vboot. BUG=chrome-os-partner:58666 TEST=boot with I2C TPM on skylake board Change-Id: I553f00a6ec25955ecc18a7616d9c3e1e7cbbb8ca Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17136 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-16soc/intel/skylake: Implement Global Reset MEI messageSubrata Banik
As per ME BWG, there are two mechanism to generate a Global Reset (resets both host and Intel ME), one is through CF9h IO write of 6h or Eh with "CF9h Global Reset" (CF9GR) bit set, PMC PCI offset ACh[20]. Another is to issue the Global Reset MEI message. Because any attempts to cause global reset without synchronizing the two sides might cause unwanted side effects, such as unwritten flash data that will get destroyed if the host were to cause a global reset without informing Intel ME firmware, the recommended method is to send a Global Reset MEI message when the following conditions are met: The PCH chipset firmware just needs to complete the Intel ME Interface #1 initialization and check the Intel ME HFSTS state if Intel ME is not in ERROR state and is accepting MEI commands then firmware should be able to use Global Reset MEI message to trigger global reset. Furthermore, if Intel ME is in ERROR state, BIOS can use I/O 0xCF9 write of 0x06 or 0x0E command with PCH ETR3 register bit [20] to perform the global reset. BUG=none BRANCH=none TEST=Verified Global Reset MEI message is able to perform platform global issue in ME good state. Change-Id: If326a137eeadaa695668b76b84c510e12c546024 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16902 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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