| Age | Commit message (Expand) | Author |
|---|
| 2020-03-04 | src: capitalize 'PCIe' | Elyes HAOUAS |
| 2020-02-24 | treewide: Capitalize 'CMOS' | Elyes HAOUAS |
| 2020-01-29 | soc/intel/skylake/acpi/dptf: Remove processor throttling controls | Wim Vervoorn |
| 2020-01-26 | soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet | Subrata Banik |
| 2020-01-26 | soc/intel/skylake: Add _SEG/_UID name variables | Subrata Banik |
| 2020-01-26 | soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device | Subrata Banik |
| 2020-01-24 | soc/intel/skylake: Remove unused ICH memory reference | Subrata Banik |
| 2020-01-24 | soc/intel/skylake: Move pci_irqs.asl from SA to PCH | Subrata Banik |
| 2020-01-18 | soc/intel/{skylake,common}/acpi/dptf/thermal.asl: Prevent iasl remarks | Wim Vervoorn |
| 2020-01-10 | soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper | Subrata Banik |
| 2020-01-07 | soc/intel/{apl,cnl,icl,skl,tgl}: Clean up SA ASL code | Subrata Banik |
| 2019-12-17 | soc/intel/skylake: Add irq 11 to the LNK* _PRS | Wim Vervoorn |
| 2019-12-17 | src: Conditionally include TEVT | Frans Hendriks |
| 2019-11-15 | soc/intel/skylake/acpi/dptf: Disable DTRP when no DPTF_TSRX_SENSOR_ID is defined | Wim Vervoorn |
| 2019-11-01 | soc/intel/{cnl,icl,skl}: Move ipu.asl into common/block/acpi | Subrata Banik |
| 2019-11-01 | soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi | Subrata Banik |
| 2019-11-01 | soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi | Subrata Banik |
| 2019-10-31 | soc/intel/skylake: Remove unused ASL debug options | Subrata Banik |
| 2019-10-31 | soc/intel/{cnl,icl,skl}: Remove unused SMI opregion | Subrata Banik |
| 2019-10-25 | soc/intel: Drop wrong _ADR objects | Elyes HAOUAS |
| 2019-08-30 | soc/intel/skl/acpi: add description for missing PCIe ports | Maxim Polyakov |
| 2019-06-08 | src/soc/intel/skylake/acpi: Remove Return for PS0/3 | Christian Walter |
| 2019-03-08 | coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) | Julius Werner |
| 2018-11-30 | cpu/intel/common: Use a common acpi/cpu.asl file | Arthur Heymans |
| 2018-11-30 | soc/intel/skylake: Rework acpi/cpu.asl | Arthur Heymans |
| 2018-11-15 | soc/intel/skylake/acpi/dptf: Add support for Multi-DPTF Profile | Karthikeyan Ramasubramanian |
| 2018-11-15 | ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT config | Karthikeyan Ramasubramanian |
| 2018-10-08 | src: Use tabs for indentation | Elyes HAOUAS |
| 2018-10-02 | soc/intel/skylake: Fix spelling mistake | Subrata Banik |
| 2018-10-02 | soc/intel/skylake: Replace white space with tab | Subrata Banik |
| 2018-08-21 | soc/intel/skylake: Remove unsupported sleepstates in ACPI table | Lucas Chen |
| 2018-08-13 | soc/intel/skylake: use unique _uid | Matt Delco |
| 2018-05-15 | soc/intel/skylake: check DPTF_TSR1_ACTIVE_AC* in _ACx methods | John Su |
| 2018-05-01 | chromeec platforms: Update ACPI thermal event handler call | Martin Roth |
| 2018-04-17 | soc/intel/skylake: check DPTF_TSR0_ACTIVE_AC* in _ACx methods | Frank Wu |
| 2018-03-30 | soc/intel/skylake: Save/restore GMA OpRegion address | Matt DeVillier |
| 2018-02-28 | skylake: Fix unwanted disablement of ACPI UPWE | Kane Chen |
| 2018-02-22 | skylake: remove legacy devices from ACPI | Patrick Georgi |
| 2018-02-16 | soc/intel/skylake: Switch to common PCR ASL | Lijian Zhao |
| 2018-01-30 | soc/intel/skylake: Add support for mode-aware DPTF | Furquan Shaikh |
| 2017-12-07 | Revert "soc/intel/skylake: Clean up SoC ASL code." | Matt DeVillier |
| 2017-10-20 | soc/intel/skylake: Add GNVS variables and include SGX ASL | Pratik Prajapati |
| 2017-10-02 | soc/intel/skylake: Use common/block/gpio | Hannah Williams |
| 2017-09-27 | soc/intel/skylake: Remove CCA object for IMGU and CIO2 devices | V Sowmya |
| 2017-08-10 | soc/intel/skylake: Enable UART debug controller on S3 resume | Furquan Shaikh |
| 2017-08-08 | soc/intel: Remove ACPI notification for fan speed change | Sumeet Pawnikar |
| 2017-07-12 | Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3" | Subrata Banik |
| 2017-07-12 | soc/intel/skylake: Perform PCR read after all PCR write | Subrata Banik |
| 2017-06-27 | soc/intel/skylake: storage: Use word access for power state registers | Duncan Laurie |
| 2017-06-27 | soc/intel/skylake: storage: Add 2ms delay before exiting D3 | Duncan Laurie |
