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path: root/src/soc/intel/skylake/bootblock/pch.c
AgeCommit message (Expand)Author
2018-03-09soc/intel/skylake: Move PCR DMI programming into bootblockSubrata Banik
2017-11-15soc/intel/skylake: Make use of common CSE code for skylakeSubrata Banik
2017-10-05soc/intel/skylake: Add support in SKL for PMC common codeShaunak Saha
2017-10-03soc/intel/skylake: Enable common LPC IPRavi Sarawadi
2017-07-11soc/intel/skylake: Fix PMC address range setup for PCH-HNico Huber
2017-07-11soc/intel/skylake: Set generic I/O decode ranges earlyNico Huber
2017-05-09soc/intel/skylake: Use intel/common/block/smbus codeAamir Bohra
2017-05-02soc/intel/skylake: Clean up code by using common FAST_SPI moduleBarnali Sarkar
2017-04-28soc/intel/skylake: Use ITSS common codeBora Guvendik
2017-04-10soc/intel/skylake: Use RTC common codeSubrata Banik
2017-04-10soc/intel/skylake: Use common PCR moduleSubrata Banik
2017-03-28soc/pci_devs.h: Use consistent naming in soc/pci_devs.hSubrata Banik
2017-03-17soc/intel/skylake: Fix remaining issues detected by checkpatchLee Leahy
2017-03-17soc/intel/skylake: Wrap lines at 80 columnsLee Leahy
2016-11-30soc/skylake: Move IO decode range out from pch_lpc_initTeo Boon Tiong
2016-10-27skylake: Prepare GPE for use in bootblockDuncan Laurie
2016-10-16soc/intel/skylake: Enable HECI BAR for ME communicationSubrata Banik
2016-08-18soc/intel/skylake: Move bootblock specific code from skylake/romstageNaresh G Solanki
2016-08-18skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early initRizwan Qureshi
2016-07-28soc/intel/skylake: Add C entry bootblock supportSubrata Banik
2016-02-04intel/skylake: unconditionally set SPI controller BARAaron Durbin
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-07-16soc/intel: Add Skylake SOC supportLee Leahy
2015-07-16soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy