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path: root/src/soc/intel/skylake/bootblock
AgeCommit message (Expand)Author
2017-05-18intel/common/block/i2c: Add common block for I2C and use the same in SoCsRizwan Qureshi
2017-05-09soc/intel/skylake: Use intel/common/block/smbus codeAamir Bohra
2017-05-02soc/intel/skylake: Clean up code by using common FAST_SPI moduleBarnali Sarkar
2017-04-28soc/intel/skylake: Use ITSS common codeBora Guvendik
2017-04-25soc/intel: Unify `timestamp.inc`Paul Menzel
2017-04-25lib: provide clearer devicetree semanticsAaron Durbin
2017-04-24soc/intel/skylake: Add ID's for Kabylake-RNaresh G Solanki
2017-04-11soc/intel/skylake: Use intel/common/uart driverAamir Bohra
2017-04-11soc/intel/skylake: Use LPSS common libraryAamir Bohra
2017-04-10soc/intel/skylake: Use RTC common codeSubrata Banik
2017-04-10soc/intel/skylake: Use common PCR moduleSubrata Banik
2017-04-06soc/intel/skylake: Add support for GSPI controllerFurquan Shaikh
2017-03-28soc/intel/skylake: Clean up code by using common System Agent moduleSubrata Banik
2017-03-28soc/pci_devs.h: Use consistent naming in soc/pci_devs.hSubrata Banik
2017-03-28soc/intel/common/block: Add cache as ram init and teardown codeSubrata Banik
2017-03-24soc/intel/skylake: Use C entry code for MTRR programmingSubrata Banik
2017-03-17soc/intel/skylake: Fix remaining issues detected by checkpatchLee Leahy
2017-03-17soc/intel/skylake: Wrap lines at 80 columnsLee Leahy
2017-03-17soc/intel/skylake: Add int to unsignedLee Leahy
2017-03-06soc/intel/skylake: Clean up CPU codeSubrata Banik
2017-02-16soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO...Sooi, Li Cheng
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
2016-11-30soc/skylake: Move IO decode range out from pch_lpc_initTeo Boon Tiong
2016-11-28soc/intel/skylake: Initialize UART based on CONFIG_UART_DEBUGTeo Boon Tiong
2016-11-11soc/intel/common/lpss_i2c: simplify API and use common config structureAaron Durbin
2016-11-07soc/intel/skylake: Add device id for PCH-YNaresh G Solanki
2016-10-27skylake: Prepare GPE for use in bootblockDuncan Laurie
2016-10-16soc/intel/skylake: Enable HECI BAR for ME communicationSubrata Banik
2016-09-02Fix newlines at the end of filesMartin Roth
2016-08-30soc/intel/skylake: Include Kabylake specific IGD Device IDsBarnali Sarkar
2016-08-18soc/intel/skylake: Correct Cache as ram sizeRizwan Qureshi
2016-08-18soc/intel/skylake: Move bootblock specific code from skylake/romstageNaresh G Solanki
2016-08-18skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early initRizwan Qureshi
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
2016-07-28intel/fsp1_1: Add C entry support to locate FSP Temp RAM InitSubrata Banik
2016-07-28soc/intel/skylake: Add C entry bootblock supportSubrata Banik
2016-07-28soc/intel/skylake: Do cache as ram and prepare for C entrySubrata Banik
2016-04-14soc/intel: Update license headersMartin Roth
2016-02-04intel/skylake: unconditionally set SPI controller BARAaron Durbin
2016-01-12intel/skylake: Remove check for Microcode loaded by MEMartin Roth
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-10-11skylake: Leave SPI controller enabledLee Leahy
2015-10-11skylake: SPI code cleanupLee Leahy
2015-09-09x86: bootblock: remove linking and program flow from build systemAaron Durbin
2015-08-13skylake: fix garbled patch from upstreamAaron Durbin
2015-07-29Skylake: Fix microcode reload in bootblock cpu initRizwan Qureshi
2015-07-16soc/intel: Add Skylake SOC supportLee Leahy
2015-07-16soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy