coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-06-22	soc/intel/common/block/cpu: Add option to skip coreboot AP init	Subrata Banik
2018-06-06	soc/intel/common/block: Add common chip config block	Subrata Banik
2018-06-05	soc/intel/skylake: Add option to skip coreboot MP init	Subrata Banik
2018-04-05	soc/intel/skylake: Enable VT-d and X2APIC	Nico Huber
2018-03-28	soc/intel/skylake: Limit xDCI feature when VBOOT is enabled	Duncan Laurie
2018-02-06	soc/intel/skylake: Add devicetree variable for PCIe HotPlug	Duncan Laurie
2018-02-06	soc/intel/skylake: Set PsysPmax value	Gaggery Tsai
2018-02-05	soc/intel/skylake: Set PsysPl3 and Pl4	Shelley Chen
2018-01-02	soc/intel/skylake: Add device setting for sata power optimization	Kane Chen
2017-12-22	soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support	Divya Chellap
2017-12-22	ic2/designware: Move Intel i2c logic to shared driver	Chris Ching
2017-12-14	soc/intel/skylake: Add integrated LAN config parameters	Duncan Laurie
2017-12-09	soc/intel/skylake: add acoustic noise mitigation params for FSP 1.1	Matt DeVillier
2017-12-05	soc/intel/skylake: Fix DSX_CFG macro name for AC_PRESENT	Furquan Shaikh
2017-11-30	soc/intel/skylake: Set low maximum temperature threshold for Thermal Device	Subrata Banik
2017-10-22	soc/intel/skylake: pass SataSpeedLimit param to FSP2	Matt DeVillier
2017-10-05	soc/intel/skylake: Add config for mbx command for Intersil VR C-state issues	Rizwan Qureshi
2017-10-02	soc/intel/skylake: Use common/block/gpio	Hannah Williams
2017-09-21	soc/intel/skylake: Add config for enabling LTR for PCIe Root port	Rizwan Qureshi
2017-09-06	soc/intel/skylake: Add config for enabling PCIe AER	Rizwan Qureshi
2017-08-25	soc/intel/skylake: Add LPC and SPI lock down config option	Subrata Banik
2017-08-18	include/device: Split i2c.h into three	Nico Huber
2017-07-26	soc/intel/skylake/chip.h: Provide enum values for SataMode	Nico Huber
2017-07-25	soc/intel/skylake: Skip Spi Flash Lockdown from FSP	Barnali Sarkar
2017-07-14	soc/intel/skylake: Set PsysPL2 MSR	Shelley Chen
2017-06-06	soc/intel/skylake/chip.h: Reorder declarations	Nico Huber
2017-06-06	soc/intel/skylake/chip.h: Provide some enums	Nico Huber
2017-05-18	intel/common/block/i2c: Add common block for I2C and use the same in SoCs	Rizwan Qureshi
2017-05-16	soc/intel/skylake: Add option to enable/disable EIST	Subrata Banik
2017-05-04	soc/intel/skylake: Remove unused skylake_i2c_config structure	Furquan Shaikh
2017-04-13	soc/intel/skylake: Split AC/DC settings for Deep Sx config	Duncan Laurie
2017-04-06	soc/intel/skylake: Add support for GSPI controller	Furquan Shaikh
2017-03-23	soc/intel/skylake: Add SGX initialization	Robbie Zhang
2017-03-22	soc/intel/skylake: Add option to disable host reads to PMC XRAM	Rizwan Qureshi
2017-03-22	soc/intel/skylake: Add configs for enabling DCI and TraceHub	Aamir Bohra
2017-03-17	soc/intel/skylake: Wrap lines at 80 columns	Lee Leahy
2017-03-17	soc/intel/skylake: Add int to unsigned	Lee Leahy
2017-03-08	intel/skylake: Add devicetree settings for acoustic noise mitigation	Duncan Laurie
2017-03-04	soc/intel/skylake: indicate voltage margining enabled/disabled	Rizwan Qureshi
2017-02-23	soc/intel/skylake: Enable Systemagent IMGU	Rizwan Qureshi
2017-02-18	soc/intel/skylake: add PrmrrSize to chip config	Robbie Zhang
2016-11-11	soc/intel/common/lpss_i2c: simplify API and use common config structure	Aaron Durbin
2016-11-11	soc/intel/skylake: move i2c voltage config to own variable	Aaron Durbin
2016-11-09	soc/intel/skylake: fix memory access beyond array bounds	Rizwan Qureshi
2016-10-26	intel/skylake: Add support to enable wake-on-usb attach/detach	Furquan Shaikh
2016-09-19	soc/intel/skylake: Add FSP 2.0 support in ramstage	Naresh G Solanki
2016-09-15	soc/intel/skylake: Add FSP 2.0 support in romstage	Barnali Sarkar
2016-08-08	skylake/devicetree: Add PIRQ Routing programming	Barnali Sarkar
2016-07-01	skylake: Generate ACPI timing values for I2C devices	Duncan Laurie
2016-06-09	skylake: Support common LPSS I2C driver	Duncan Laurie