coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2017-08-18	include/device: Split i2c.h into three	Nico Huber
2017-07-26	soc/intel/skylake/chip.h: Provide enum values for SataMode	Nico Huber
2017-07-25	soc/intel/skylake: Skip Spi Flash Lockdown from FSP	Barnali Sarkar
2017-07-14	soc/intel/skylake: Set PsysPL2 MSR	Shelley Chen
2017-06-06	soc/intel/skylake/chip.h: Reorder declarations	Nico Huber
2017-06-06	soc/intel/skylake/chip.h: Provide some enums	Nico Huber
2017-05-18	intel/common/block/i2c: Add common block for I2C and use the same in SoCs	Rizwan Qureshi
2017-05-16	soc/intel/skylake: Add option to enable/disable EIST	Subrata Banik
2017-05-04	soc/intel/skylake: Remove unused skylake_i2c_config structure	Furquan Shaikh
2017-04-13	soc/intel/skylake: Split AC/DC settings for Deep Sx config	Duncan Laurie
2017-04-06	soc/intel/skylake: Add support for GSPI controller	Furquan Shaikh
2017-03-23	soc/intel/skylake: Add SGX initialization	Robbie Zhang
2017-03-22	soc/intel/skylake: Add option to disable host reads to PMC XRAM	Rizwan Qureshi
2017-03-22	soc/intel/skylake: Add configs for enabling DCI and TraceHub	Aamir Bohra
2017-03-17	soc/intel/skylake: Wrap lines at 80 columns	Lee Leahy
2017-03-17	soc/intel/skylake: Add int to unsigned	Lee Leahy
2017-03-08	intel/skylake: Add devicetree settings for acoustic noise mitigation	Duncan Laurie
2017-03-04	soc/intel/skylake: indicate voltage margining enabled/disabled	Rizwan Qureshi
2017-02-23	soc/intel/skylake: Enable Systemagent IMGU	Rizwan Qureshi
2017-02-18	soc/intel/skylake: add PrmrrSize to chip config	Robbie Zhang
2016-11-11	soc/intel/common/lpss_i2c: simplify API and use common config structure	Aaron Durbin
2016-11-11	soc/intel/skylake: move i2c voltage config to own variable	Aaron Durbin
2016-11-09	soc/intel/skylake: fix memory access beyond array bounds	Rizwan Qureshi
2016-10-26	intel/skylake: Add support to enable wake-on-usb attach/detach	Furquan Shaikh
2016-09-19	soc/intel/skylake: Add FSP 2.0 support in ramstage	Naresh G Solanki
2016-09-15	soc/intel/skylake: Add FSP 2.0 support in romstage	Barnali Sarkar
2016-08-08	skylake/devicetree: Add PIRQ Routing programming	Barnali Sarkar
2016-07-01	skylake: Generate ACPI timing values for I2C devices	Duncan Laurie
2016-06-09	skylake: Support common LPSS I2C driver	Duncan Laurie
2016-06-09	skylake: Move I2C bus configuration to separate structure	Duncan Laurie
2016-05-31	skylake: Add SD card device to configure card detect GPIO	Duncan Laurie
2016-05-31	skylake: Add GPE header file to chip.h	Duncan Laurie
2016-05-09	soc/intel/skylake: Enable another VR mailbox command for certain boards	Subrata Banik
2016-03-12	soc/intel/skylake: add option to statically clock gate 8254 timer	Aaron Durbin
2016-03-12	soc/intel/skylake: add option to enable VR specific mailbox cmd	Rizwan Qureshi
2016-03-01	Skylake: Support Intel Speed Shift Technology based on config	Subrata Banik
2016-02-04	intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown	Archana Patni
2016-01-22	intel/skylake: Thermal Design Power PL1 and PL2 Config Changes	pchandri
2016-01-19	intel/skylake: Adding provision to set voltages to the I2C ports	Naresh G Solanki
2016-01-18	intel/skylake: Change in UPD name from SkipMpInit to FspSkipMpInit	Barnali Sarkar
2016-01-18	intel/skylake: Remove unused devicetree configuration variables	Duncan Laurie
2016-01-18	intel/skylake: Add devicetree setting for DDR frequency limit UPD	Duncan Laurie
2016-01-17	intel/skylake: disable heci1 if psf is unlocked	Archana Patni
2016-01-16	intel/skylake: Add VrConfig UPD parameters from coreboot	Rizwan Qureshi
2016-01-16	intel/skylake: Enable SkipMpInit token	Rizwan Qureshi
2016-01-15	intel/skylake: More UPD params are added for PCH policy in FSP	Rizwan Qureshi
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-27	intel/skylake: Clean up USB configuration in devicetree	Duncan Laurie
2015-10-27	intel/skylake: IRQ programming through UPD	Subrata Banik
2015-10-27	intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params update	Rizwan Qureshi