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coreboot
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broadwell_refcode
e6230
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Some coreboot project code with my work
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intel
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skylake
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chip_fsp20.c
Age
Commit message (
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Author
2017-03-22
soc/intel/skylake: Add option to disable host reads to PMC XRAM
Rizwan Qureshi
2017-03-17
soc/intel/skylake: Fix remaining issues detected by checkpatch
Lee Leahy
2017-03-08
intel/skylake: Add devicetree settings for acoustic noise mitigation
Duncan Laurie
2017-03-04
soc/intel/skylake: indicate voltage margining enabled/disabled
Rizwan Qureshi
2017-02-23
soc/intel/skylake: Enable Systemagent IMGU
Rizwan Qureshi
2017-02-22
soc/intel/skylake: Fix broken suspend-resume
Furquan Shaikh
2017-02-19
soc/intel/skylake: Disable s0ix if not enabled in devicetree
Duncan Laurie
2017-02-14
soc/intel/skylake: Perform CPU MP Init before FSP-S Init
Subrata Banik
2017-02-14
Revert: soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1
Duncan Laurie
2017-01-20
soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1
Barnali Sarkar
2017-01-11
skylake: Do not pass VBT to FSP if display init not required
Duncan Laurie
2016-12-01
romstage_handoff: add helper to determine resume status
Aaron Durbin
2016-11-30
soc/intel/skylake: Use SendVrMbxCmd1 for FSP 2.0
Rizwan Qureshi
2016-11-30
soc/intel/skylake: Disable Legacy PME for Root ports
Naresh G Solanki
2016-11-28
soc/intel/skylake: Add USB Port Over Current (OC) Pin programming
Subrata Banik
2016-11-21
fsp2_0: implement stage cache for silicon init
Brandon Breitenstein
2016-11-11
soc/intel/skylake: move i2c voltage config to own variable
Aaron Durbin
2016-09-19
soc/intel/skylake: Add FSP 2.0 support in ramstage
Naresh G Solanki
2016-08-31
skylake: Add initial FSP2.0 support
Rizwan Qureshi