coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-12-02	soc/intel/skylake: Fix compilation under x86_64	Patrick Rudolph
2020-10-03	soc/intel: Move soc_pch_pirq_init() to common code	Subrata Banik
2020-09-30	soc/intel/skylake: Align soc_pch_pirq_init() with CNL	Subrata Banik
2020-07-26	skylake boards: Factor out copy-pasted PIRQ routes	Angel Pons
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	soc/intel/skylake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-10-02	intel/skylake: Refactor IRQ assignments	Kyösti Mälkki
2019-07-18	soc/intel: Use config_of()	Kyösti Mälkki
2019-07-04	soc/intel: Replace uses of dev_find_slot()	Kyösti Mälkki
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2018-10-02	soc/intel/skylake: Fix spelling mistake	Subrata Banik
2018-06-04	soc/intel/skylake: Get rid of device_t	Elyes HAOUAS
2018-02-20	src/soc: Fix various typos	Jonathan Neuschäfer
2017-10-03	soc/intel/skylake: Enable common LPC IP	Ravi Sarawadi
2017-03-28	soc/pci_devs.h: Use consistent naming in soc/pci_devs.h	Subrata Banik
2016-09-19	soc/intel/skylake: Add FSP 2.0 support in ramstage	Naresh G Solanki