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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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soc
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intel
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skylake
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romstage
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romstage.c
Age
Commit message (
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Author
2015-10-11
soc/intel/common: remove chipset specific calls
Aaron Durbin
2015-10-11
intel SOC common: Remove unused parameters
Lee Leahy
2015-09-23
chromeos: vboot and chromeos dependency removal for sw write protect state
Paul Kocialkowski
2015-09-08
Skylake:Set DISB inside romstage after mrc init
Dhaval Sharma
2015-08-29
intel/skylake: Fix RMT disable of saved training data
Duncan Laurie
2015-08-29
intel/skylake: Force full memory train if RMT is enabled
Duncan Laurie
2015-08-29
fsp raminit: Add romstage_params to soc_memory_init_params
Duncan Laurie
2015-08-19
skylake: Update Memory and Silicon Init params
Rizwan Qureshi
2015-08-14
skylake: pass IED_REGION_SIZE Kconfig to FSP
Aaron Durbin
2015-08-13
skylake: fix serial port with new code base
Aaron Durbin
2015-07-24
skylake: Fix building without serial console
Duncan Laurie
2015-07-21
Skylake: Only support UART2 as debug port, clean up the rest
Naveen Krishna Chatradhi
2015-07-21
skylake: honor pcie root port settings already in chip.h
Aaron Durbin
2015-07-21
skylake: Show SPI controller if enabled in devicetree.cb
Duncan Laurie
2015-07-16
soc/intel: Add Skylake SOC support
Lee Leahy
2015-07-16
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC
Lee Leahy