summaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake/romstage
AgeCommit message (Expand)Author
2016-06-09skylake: Support common LPSS I2C driverDuncan Laurie
2016-02-29skylake: Increase IGD stolen size to 64MBDuncan Laurie
2016-02-15skylake: Check for power failure when WAK_STS is not setDuncan Laurie
2016-02-04intel/skylake: implement vboot_platform_prepare_reboot()Aaron Durbin
2016-02-04intel/skylake: implement vboot_platform_is_resuming()Aaron Durbin
2016-01-29intel/skylake: Implement native Cache-as-RAM (CAR)Subrata Banik
2016-01-19intel/skylake: Disable SaGv in recovery modeharidhar
2016-01-18intel/skylake: Add devicetree setting for DDR frequency limit UPDDuncan Laurie
2016-01-15intel/skylake: Update UPD parameters as per FSP 1.8.0Barnali Sarkar
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-27FSP 1.1: Replace soc_ prefix with fsp_Lee Leahy
2015-10-27intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params updateRizwan Qureshi
2015-10-11skylake: add support for verstageAaron Durbin
2015-10-11intel fsp1_1: prepare for romstage vboot verification splitAaron Durbin
2015-10-11soc/intel/common: remove chipset specific callsAaron Durbin
2015-10-11intel SOC common: Remove unused parametersLee Leahy
2015-09-23chromeos: vboot and chromeos dependency removal for sw write protect statePaul Kocialkowski
2015-09-08Skylake:Set DISB inside romstage after mrc initDhaval Sharma
2015-09-08skylake: Remove dead codeLee Leahy
2015-09-08skylake: move flash_controller.h to the proper placeAaron Durbin
2015-08-29intel/skylake: Implement HW Sequence based WP status read functionalityBarnali Sarkar
2015-08-29intel/skylake: Fix RMT disable of saved training dataDuncan Laurie
2015-08-29intel/skylake: Force full memory train if RMT is enabledDuncan Laurie
2015-08-29fsp raminit: Add romstage_params to soc_memory_init_paramsDuncan Laurie
2015-08-19skylake: Update Memory and Silicon Init paramsRizwan Qureshi
2015-08-14skylake: pass IED_REGION_SIZE Kconfig to FSPAaron Durbin
2015-08-14skylake: use native gpio configuration for uartAaron Durbin
2015-08-13skylake: fix serial port with new code baseAaron Durbin
2015-07-24skylake: Fix building without serial consoleDuncan Laurie
2015-07-21skylake: add global reset cause registers to power stateAaron Durbin
2015-07-21skylake: take into account deep s3 in power failure checkAaron Durbin
2015-07-21skylake: read out and report full width of gen_pmcon registersAaron Durbin
2015-07-21intel/skylake: support 32bit uart8250_mem driver in romstageNaveen Krishna Chatradhi
2015-07-21Skylake: Initialize GPIOs for UART2rsatapat
2015-07-21Skylake: Only support UART2 as debug port, clean up the restNaveen Krishna Chatradhi
2015-07-21skylake: honor pcie root port settings already in chip.hAaron Durbin
2015-07-21skylake: Show SPI controller if enabled in devicetree.cbDuncan Laurie
2015-07-16soc/intel: Add Skylake SOC supportLee Leahy
2015-07-16soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 06:25:30 +0000