| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-08-20 | soc/intel/common/block: Move common uart function to block/uart | Subrata Banik |
| 2018-05-08 | soc/intel/skylake: Support PCH UART 0 and 1 for console | Duncan Laurie |
| 2017-12-07 | soc/intel/skylake: Clean up UART code | Aamir Bohra |
| 2017-08-21 | soc/intel/skylake: Add support for all UART port index | Subrata Banik |
| 2017-08-10 | soc/intel/skylake: Enable UART debug controller on S3 resume | Furquan Shaikh |
| 2017-05-09 | soc/intel/skylake: Use common/blocks/uart code | Aamir Bohra |
| 2017-02-16 | soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO... | Sooi, Li Cheng |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-08-13 | skylake: fix serial port with new code base | Aaron Durbin |
| 2015-07-24 | skylake: Fix building without serial console | Duncan Laurie |
| 2015-07-21 | Skylake: Only support UART2 as debug port, clean up the rest | Naveen Krishna Chatradhi |
| 2015-07-16 | soc/intel: Add Skylake SOC support | Lee Leahy |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |