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2020-12-17soc/intel/skylake: Drop duplicate PmConfigPciClockRun configurationBenjamin Doron
coreboot already unconditionally enables CLKRUN_EN in SoC common code. Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN] of LPC is still enabled. Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config optionShreesh Chhabbi
SF Mask MSRs' Programming which was done under this config selection will be moved under a new config option called CAR_HAS_SF_MASKS. This segregates the eNEM programming sequence based on sub features supported in each processor. Bug=b:171601324 BRANCH=volteer Test=Build volteer build and boot on Delbin EVT. Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop always-zero ProbelessTrace dt settingAngel Pons
This seems to be a debugging option. Since unset devicetree options default to zero, drop the setting. If it is needed in the future, a user-visible Kconfig option would probably make more sense. Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop always-zero PowerLimit4 dt settingAngel Pons
Unset devicetree settings default to zero, so the devicetree setting can be removed. Looks like no one needs it anyway. Change-Id: Iad94538c5465347b37a99c6c9f20988168661593 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop never-set DdrFreqLimit dt settingAngel Pons
Only Google Eve uses a non-zero value, but it overwrites in C code. Drop the devicetree setting, since no mainboard uses it. Change-Id: I14e0e0cb9baa2b1f8f795e6bc6ffbee300f2243d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop unreferenced PttSwitch dt settingAngel Pons
The value for this setting is not used anywhere. Drop it. Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: I76aa2327d440394a9176c023bc95fb34e713741e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48571 Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/intel/common/block/lpc: Move southbridge_write_acpi_tables declarationMarc Jones
Move the southbridge_write_acpi_tables declaration from acpi.h to common lpc_lib.h, as common LPC is always the caller. This removes a duplicate declaration since all soc/intel devices use common LPC, but not all use common ACPI. The southbridge_write_acpi_tables function is defined in acpi.c with the other acpi functions. Note that this would have the reverse problem if there is ever a non-common LPC device. Change-Id: I0590a028b11f34e423d8f0007e0653037b0849a0 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48251 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/intel/common: Adapt XHCI elog driver for reuseTim Wawrzynczak
Currently this XHCI driver assumes the PCH XHCI controller, but the TCSS or North XHCI block has a similar enough PCI MMIO structure to make this code mostly reusable. 1) Rename everything to drop the `pch_` prefix 2) xhci_update_wake_event() now takes in a pci_devfn_t for the XHCI controller 3) soc_get_xhci_usb_info() also now takes a pci_devfn_t for the XHCI controller BUG=b:172279037 TEST=plug in USB keyboard while in S0, enter S0ix and verify entry via EC; type on keyboard, verify it wakes up, eventlog contains: 39 | 2020-12-10 09:40:21 | S0ix Enter 40 | 2020-12-10 09:40:42 | S0ix Exit 41 | 2020-12-10 09:40:42 | Wake Source | PME - XHCI (USB 2.0 port) | 1 42 | 2020-12-10 09:40:42 | Wake Source | GPE # | 109 which verifies it still functions for the PCH XHCI controller Change-Id: I9f28354e031e3eda587f4faf8ef7595dce8b33ea Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47411 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/intel/common/dmi: Move DMI defines into DMI driver headerSrinidhi N Kaushik
Move definitions of DMI control register and Secure Register Lock (SRL) bit into common/block/dmi driver header file. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Iefee818f58f399d4a127662a300b6e132494bad0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48257 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08soc/intel/skylake: Shorten SATA mode enum value namesFelix Singer
The Skylake FSP isn't used by coreboot anymore. Therefore, drop the misleading comment and the "KBLFSP" extension from the names of these enums. Also, drop the "MODE" extension to make their names shorter in general, since it doesn't add any more value. Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: If37d40e4e1dfd11e9315039acde7cafee0ac60f0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48377 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08soc/intel/skylake: Restore alphabetical order of Kconfig selectsFelix Singer
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I6a5c694a9686a5435aa5c64647286a6017f9aa13 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48376 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-07soc/intel/skl: set PEG port state to autoMichael Niewöhner
Setting PegXEnable to 1, statically enables the PEG ports, which blocks the SoC from going to deeper PC states. Instead, set the state to "auto" (2), so the port gets disabled, when no device was detected. Note: Currently, this only works with the AST PCI bridge disabled or the VGA jumper set to disabled on coreboot, while it works on vendor in any case. The reason for this is still unclear. Test: powertop on X11SSM-F shows SoC in PC8 like on vendor firmware instead of just PC3 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I3933a219b77d7234af273217df031cf627b4071f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-04soc/intel/{skl,cnl}: add NMI_{EN,STS} registersMichael Niewöhner
Add NMI_EN and NMI_STS registers, so they can be configured for using NMI gpios. References: - CMP-LP: Intel doc# 615146-1.2 - CMP-H: Intel doc# 620855-002 - SPT-H: Intel doc# 332691-003 - SPT-LP: Intel doc# 334659-005 - CNP-H: Intel doc# 337868-002 Test: trigger NMI via gpio on Supermicro X11SSM-F did not work before but now makes the Linux kernel complain about a NMI. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I4d57ae89423bdaacf84f0bb0282bbb1c9df94598 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48091 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04soc/intel/common/block/gpio: add code for NMI enablingMichael Niewöhner
Especially server boards, like the Supermicro X11SSM-F, often have a NMI button and NMI functionality that can be triggered via IPMI. The purpose of this is to cause the OS to create a system crashdump from a hang system or for debugging. Add code for enabling NMI interrupts on GPIOs configured with PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI function was copied and adapted. The `pad_community` struct gained two variables for the registers. Also register the NMI for LINT1 in the MADT in accordance to ACPI spec. Test: Linux detects the NMI correctly in dmesg: [ 0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03soc/intel/skylake: Add chipset devicetreeFelix Singer
Set most of the devices to off to keep current behaviour. Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-03src: Remove redundant use of ACPI offset(0)Elyes HAOUAS
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02soc/intel/skylake: Fix compilation under x86_64Patrick Rudolph
Change-Id: I37382ab06a8f1760e955d1ec76a6a00958b05999 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48177 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02soc/intel/skylake: Map VBIOS IDsPaul Menzel
The extracted VBIOS Option ROM ships the same ID for several generations, not matching the ID on the hardware resulting in a mismatch, and coreboot does not run the Option ROM. PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Add the appropriate mappings. TEST=coreboot runs the ROM on the TUXEDO Book BU1406. Change-Id: Ia167d91627a7ff1b329ea75f150b3ce95c0acccb Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43853 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/intel/skylake: Fix commentFelix Singer
mainboard_silicon_init_params() is *not* meant for configuring GPIOs. It should only be used to configure FSP options, which can not be configured elsewhere. Change-Id: Ia92d0d173af9c67600e93b473480967304772998 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48008 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29soc/intel: Configure P2SB before other PCH controllersFurquan Shaikh
This change updates bootblock_pch_early_init() to perform P2SB configuration before any other PCH controllers are initialized. This is done because the other controllers might perform PCR settings which requires the PCR base address to be configured. As the PCR base address configuration happens during P2SB initialization, this change moves the p2sb init calls before any other PCH controller initialization. BUG=b:171534504 Change-Id: I485556be003ff5338b4e2046768fe4f6d8a619a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47885 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-28soc/intel/skl: correct OC pin skip value for disabled usb portsMichael Niewöhner
Commit 056d552 introduced a bug where 0xFF gets set as OC pin value to supposedly skip programming an OC pin for a disabled USB port. While the value is correct for the other platforms, Skylake uses 0x08 for this purpose. Correct this by using the enum value OC_SKIP (0x08) instead. Change-Id: I41a8df3dce3712b4ab27c4e6e10160b2207406d1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-24soc/intel/skylake: Support NHLT 1ch DMICBenjamin Doron
Allows advertising support for a 1ch array DMIC in the NHLT table. Boards use the NHLT if a microphone is connected to the DSP. Tested on an Acer Aspire VN7-572G (Skylake-U) on Windows 10. A custom ALSA topology will be required for Linux. Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-24soc/intel/skylake: Use correct NHLT_PDM_DEV definitionBenjamin Doron
According to the NHLT specification[1], PDM_DEV is defined as "1" on Kabylake based platforms. coreboot currently sets it to "0" on all platforms. Add an entry to the enum and use it to define NHLT_PDM_DEV for Kabylake. "Device Type" will resume from "2" on all platforms, but entries are currently reserved. Tested on an Acer Aspire VN7-572G (Skylake-U), which has a 1ch array DMIC, on Windows 10. 1. https://01.org/sites/default/files/595976_intel_sst_nhlt.pdf Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45010 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22soc/intel/block/pmc: Only include the PCI driver when it is not hiddenArthur Heymans
On more recent Intel platforms FSP-S hides the PMC PCI device and the driver is broken for those devices so don't include it at all. Change-Id: I784be250698ec1c1e9b3b766cf1bcca55730c021 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-13soc/intel/{skl,cnl}: replace PM ACPI timer dt option by KconfigMichael Niewöhner
Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and set the FSP option for PM ACPI timer enablement from its value instead of using the old devicetree option. Also drop the obsolete devicetree option from soc code and from the mainboards and add a corresponding Kconfig entry instead. Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/{skl,cnl}: drop duplicate PM ACPI timer disablingMichael Niewöhner
FSP already disables the PM ACPI timer, when EnableTcoTimer=0. Test: clevo/l140cu and supermicro/x11ssm-f have the PM ACPI timer disable bit set when EnableTcoTimer=0. Change-Id: If370d3acf87ae6d1d7c64bf27228877cdd92ab2d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-09soc/intel/skylake: Enable PCH thermal depending on devicetreeBenjamin Doron
Hook up PCH thermal subsystem configuration to devicetree. Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-04soc/intel/skl,acpi/acpigen: convert global CPPC package to local oneMichael Niewöhner
Move the global CPPC package \GCPC to the first logical core CP00 and adapt the reference in the other cores. This is cleaner and avoids confusion. Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-02soc/intel: Use of common reset code blockSubrata Banik
This patch removes all redundant reset code block from each SoC and make use of common reset code block(fsp_reset.c) based on SOC_INTEL_COMMON_FSP_RESET. Respective SoC Kconfig to choose correct FSP global reset type as per FSP integration guide. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28soc/intel: deduplicate ACPI timer emulationMichael Niewöhner
The code for enabling ACPI timer emulation is the same for the SoCs SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to common code. APL differs in not having the delay settings. However, the bits are marked as "spare" and BWG mentions there are no "reserved bit checks done". Thus, we can write them unconditionally without any effect. Note: The ACPI timer emulation can only be used by SoCs with microcode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-26soc/intel/skl: replace conditional on dt option reading CPUID for CPPCMichael Niewöhner
Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead of relying on the devicetree option `speed_shift_enable`, that is going to be dropped. Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46461 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26soc/intel: drop unneeded ISST configuration codeMichael Niewöhner
The code configuring ISST (Intel SpeedShift Technology) sets the ISST capability bits in CPUID.06H:EAX. It does *not* activate HWP (Hardware P-States), which shall be done by the OS only. Since the capability is enabled by default (opt-out), there is nothing to do for us in the enabled-case. Practically speaking, there is no value at all in disabling the capability, since one can configure the OS to not enable HWP if that is desired. The two other bits for EPP and HWP interrupt that were set by the code are not set anymore, too. It was tested, on three platforms so far (CML-U, KBL-H, SKL-U), that these are set as well by default in the MSRs reset value (0x1cc0). To reduce complexity and duplicated code without actual benefit, this code gets dropped. The remaining dt option will be dropped in CB:46462. Test: Linux on Supermicro X11SSM-F detects and enables HWP: [ 0.415017] intel_pstate: HWP enabled Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46460 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26src: Include <arch/io.h> when appropriateElyes HAOUAS
Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24{cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. This change just moves the code. Rework is done in CB:46588. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21{cpu,soc}/intel: replace AES-NI locking by common implemenation callMichael Niewöhner
Deduplicate code by using the new common cpu code implementation of AES-NI locking. Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21soc/intel,mb/*: get rid of legacy pad macrosMichael Niewöhner
Get rid of legacy pad macros by replacing them with their newer equivalents. TEST: TIMELESS-built board images match Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21soc/intel: convert XTAL frequency constant to KconfigMichael Niewöhner
This converts the constant for the XTAL frequency to a Kconfig option. Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21soc/intel/common: add Kconfig for PM Timer emulation supportMichael Niewöhner
Add a Kconfig for SoCs to indicate PM ACPI timer emulation support and select it by the appropriate SoCs. This Kconfig gets used in the follow-up changes. Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19soc/intel/*: drop useless XTAL shutdown qualification codeMichael Niewöhner
The XTAL shutdown (dis)qualification bit already unconditionally gets set to 1 by FSP for these platforms, making this code redundant. Change-Id: I7fa4afb0de2af1814e5b91c152d82d7ead310338 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46016 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19soc/intel/skylake: Do not let FSP set the subsystem IDsBenjamin Doron
The subsystem ID registers are read/write-once. Writes by coreboot will not take effect if FSP sets them. Note that FSP sets one device ID for the SA devices and another for PCH devices. coreboot will copy individual vendor and device IDs if subsystem is not provided. Change-Id: I9157fb69f2a49dfc08f049da4b39fbf86614ace3 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-17cpu/intel,soc/intel: drop Kconfig for hyperthreadingMichael Niewöhner
Drop the Kconfig for hyperthreading to be always able to check at runtime if hyperthreading is supported. Having a Kconfig for this doesn't have any benefit. Change-Id: Ib7b7a437d758f7fe4a09738db1eab8189290b288 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-16soc/intel/skylake: Rename PcieRpAspm devicetree configBenjamin Doron
This configuration option shares a name with the FSP UPD, but is enumerated differently. Change its name to minimise confusion about the options. Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-15soc/intel/skylake: Configure L1 substates for PCH root portsBenjamin Doron
Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration. Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-14soc/intel/skylake/cpu.c: Fix comment coding styleAngel Pons
This comment does not follow any of the styles outlined in the coding style page of the documentation. Adjust it to match the preferred style. Change-Id: Idf6d0ea69a08e378266b4256c476580889adfca8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46428 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12soc/intel: Configure PAVP at compile-timeBenjamin Doron
Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. Per the FSP default, this was always being enabled previously. Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik
This patch moves platform.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify _PIC method present inside common platform.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/{cnl,icl,skl}: Convert 'platform.asl' to ASL 2.0 syntaxSubrata Banik
Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I3fcd971402e540d91a7392ca58175eb3ecc24cec Reviewed-on: https://review.coreboot.org/c/coreboot/+/45981 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel/skylake: Align platform.asl with CNLSubrata Banik
Refer _WAK and _PTS ASL functions from common platform.asl TEST=Dump and disassemble DSDT, verify all methods present inside common platform.asl like _WAK, _PTS etc. are still there. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I625e42b3c49abbb3595a4307da5fc24850a98fbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/45980 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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