coreboot - Some coreboot project code with my work

Age	Commit message (Collapse)	Author
2020-02-09	soc/intel/tigerlake: add memory configuration support	Nick Vaccaro
	Move some of the common memory code that was being performed in mainboard into the soc to reduce redundant code going forward. BUG=b:145642089 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel and verify memory size shows 8GB. Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-13	soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig	Maulik V Vaghela
	New Kconfig for Jasperlake soc was created and fsp_param for Jasperlake has differences compared to Tigerlake. Thus renaming fsp_params.c to fsp_params_tgl.c to point out correct file as per soc selected. Also adding new file for fsp_param_jsl for Jasperlake SoC and currently its the copy of fsp_param_tgl. TODO: update files with correct fsp_params Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37267 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02	soc/intel/tigerlake: Change compilation based on TIGERLAKE_BASE	Maulik V Vaghela
	since we support JSL and TGL soc under tigerlake folder, we need to make sure all soc related files get compiled based on CONFIG_SOC_INTEL_TIGERLAKE_BASE and not only for Tigerlake. We can control soc specific file compilation through Kconfig of individual soc. Change-Id: I1a663555d0bdf7588c4e12363375e7c90629f7d9 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-11-09	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik
	Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 5.c Remove dGPU over PCIE enable Kconfig option 6. Add CPU/PCH/SA EDS document number and chapter number 7. Remove unnecessary headers from .c files based on review Tiger Lake specific changes will follow in subsequent patches. 1. Include GPIO controller delta over ICL 2. FSP-S related UPD overrides as applicable Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36087 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>