coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-04-13	acpi: Bump FADT to revision 6	Patrick Rudolph
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-12	soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table	John Zhao
2020-01-10	soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper	Subrata Banik
2019-12-31	soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADT	Meera Ravindranath
2019-11-09	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik