| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-03-12 | soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table | John Zhao |
| 2020-01-10 | soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper | Subrata Banik |
| 2019-12-31 | soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADT | Meera Ravindranath |
| 2019-11-09 | soc/intel/tigerlake: Do initial SoC commit till ramstage | Subrata Banik |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |