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This change enables the USB4/Thunderbolt common layer for Intel SOC,
and enables the Intel USB4 PCIe driver. This moves the _DSD variables
from the DSDT into the SSDT and allows them to be configured for each
board if necessary.
Change-Id: I2564512d951046e015c148db42fdaf2d4b8b81dd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44917
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add gfx.asl file for all IA SOCs to allow for graphics-related ACPI
devices and methods.
TEST=Able to build and boot TGL platform
Dump and disassemble DSDT, verify GFX0 device present as below
Device (GFX0)
{
Name (_ADR, 0x00020000) // _ADR: Address
}
Change-Id: I5560e900a77872552df1064dc3b7a8148e35d682
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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There is requirement to change PM flow for S0ix along with TBT firmware
update under device attached and no device attached scenarios. This
change invokes D3CE and D3CX in DMA _PS3 and _PS0 respectively.
BUG=b:158777291
TEST=Validated s0ix cycles for USB4 device attached and no device
attached test cases along with updated TBT firmware rev35.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Iebc8065fe4c8600960d089577608890ab12a95fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I8deaeb29abed097d536f1c3c44606a549c6af4e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch moves ish.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CML platform.
1) Dump and disassemble DSDT, verify ISHB device present inside
common ish.asl is still there with correct _ADR value.
2) Verify no ACPI error seen while running 'dmesg` from console.
CML platform:
Device (ISHB)
{
Name (_ADR, 0x00130000) // _ADR: Address
Name (_DDN, "Integrated Sensor Hub Controller") //_DDN: DOS Device Name
}
TGL/JSL platform:
Device (ISHB)
{
Name (_ADR, 0x00120000) // _ADR: Address
Name (_DDN, "Integrated Sensor Hub Controller") //_DDN: DOS Device Name
}
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I33c1649d7a632c7b147e1bf307cfb5c1dfd84c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch moves platform.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify _PIC method present inside
common platform.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch moves smbus.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify SBUS device present inside
common smbus.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ib1ae48f7ece3e521501d92c40cd551287ea2f1ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Delete SoC local copy of ipu.asl and refer from common block ipu.asl
TEST=Dump and disassemble DSDT on tglrvp, verify IPU0 device
present there.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I6a0f8a919092f7bbcd64d4791746d30fdee33894
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch moves pch_glan.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify GLAN device present inside
common pch_glan.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I479678c864eba39e5ab04f658600e8cba48198ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch moves gpio_op.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify all methods present inside
common gpio_op.asl like GRXS, GTXS etc. are still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I248f5e66994d2f3d6b0bd398347e7cf9ae7f2cc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch ensures that GRXS perform PAD_CFG0_RX_STATE mask first
and then right shift PAD_CFG0_RX_STATE_BIT to get correct GPIO number.
Change-Id: I96611936f70f79e9dc5ee9414ec68cef00d0d13a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45738
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also align GPMO ASL function with TGL.
Change-Id: Ia40af2cba9867838a1f99141481a5e78cffa0111
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Also remove unneded tab in 'picasso/Makefile.c' file.
Change-Id: Id25b2d308645c449c205b3a946f89b6b6de62a47
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds Type-C Intel Input Output Manager(IOM) device with HID
INTC1072. It provides MMIO range from 0xfbc10000 with size 0x1600.
Intel Input Output Manager(IOM) kernel driver reads relevant
information such as Type-C port status (whether a device is connected
to a Type-C port or not) and the activity type on the Type-C ports
(such as USB, Display Port, Thunderbolt) using this memory resource.
BUG=b:156016218
TEST=Able to detect USB, TBT and USB4 on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic733e831643bda6e052edf797ba0e6206eb4ddd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41762
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds Platform-Wide _OSC capabilities for native USB4
support. There is Engineering Change Request (ECR) with _OSC addition
for OSPM USB support. ACPI section 6.2.11.1.13 is modified with bit 18
as native USB4 support. The OS sets this bit to indicate support for
an OSPM-native USB4 Connection Manager which handles USB4 connection
events and link management. The OS use the _OSC mechanism and the bit
defined in this ECR to obtain configuration and connection management
capabilities of USB4 connections. This change also fixs the byte index
for the DWord-addressable field CDW3 from the capabilities buffer.
BUG=b:140645231
TEST=Check Type C device all ports connection/enumeration with SW CM.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1b561ea5a0a6b440cca3152cc150f31abf7766ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42795
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The dmesg shows unresolved symbol CDW1 with AE_NOT_FOUND error after
booting to kernel. Fix the error by properly creating the buffer field
CDW1 to cover all errors scenarios.
BUG=b:140645231
TEST=Verified no AE_NOT_FOUND error related to \_SB.OSC.CDW1.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ibfe677f87736ce1930e06b9cd649791977116012
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42693
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates platform.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for volteer.
Change-Id: I248f5e9a1e3ba4f6426167f0406073252cc6513a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42506
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds support for SW CM. Add Operating System Capabilities
(_OSC) method to enable USB/DisplayPort/Inter-domain USB4 Internet
Protocol tunneling and enable PCIe tunneling as well. Remove Connect
Topology(CNTP) command because kernel driver directly works with SW CM
Thunderbolt firmware. Update _DSD method for USB4 support across XHCI
and PCIe root ports.
BUG=b:140645231
TEST=Check Type C device all ports connection/enumeration with SW CM.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I859c5075882e40d7be30d4ba88cc825886712b74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add unique new acpi device ids for dptf for Tiger Lake soc based platforms
and update volteer speficic dsdt.asl file accordingly. The Linux kernel
driver expects these new acpi device ids for dptf functionalities.
BUG=None
BRANCH=None
TEST=Build and boot on volteer system
Change-Id: I7dbb812c0fc0f5084c98cf2752ce7ddce8e4d50e
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This change adds Hot-Plug and power management event handers(_L61 &
_L69) respectively for Thunderbolt in the GPE scope. The _L61 method
invokes sub-method HPEV to support Hot-Plug wake event from Thunderbolt
PCIe root ports. This method intercepts Presence Detect Changed
interrupt and make sure the L0s is disabled on empty slots. The _L69
method checks and clears root port's PME SCI status.
BUG=b:156435065
TEST=Verified multiple hot plug successfully with Lenovo dock.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I022cf4aa3f2ee459b9dc87849494e10755d995c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This change updates gpio_op.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
BUG=none
BRANCH=none
TEST="BUILD for Volteer"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ib54b3f7da828ce8d232fcea0639077970638f610
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This change updates pch_hda.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
BUG=none
BRANCH=none
TEST="BUILD for Volteer"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ia2bab6dcbac9eae76ac4258c44bb19425c8b5c80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This change updates camera_clock_ctl.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
BUG=none
BRANCH=none
TEST="BUILD for volteer"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: I6370e4b268331bfba5bc0392f27c560836b6ea72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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In an attempt to help reduce the amount of static ASL files that are
littered throughout the codebase, pmc.asl was converted to runtime SSDT
generation instead. If future SoCs reuse the same PMC, then this
function can be moved to soc/intel/common/block/pmc for example.
TEST=Verified the following was in the decompiled SSDT:
Scope (\_SB.PCI0)
{
Device (PMC)
{
Name (_HID, "INTC1026") // _HID: Hardware ID
Name (_DDN, "Intel(R) Tiger Lake IPC Controller")
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
0xFE000000, // Address Base
0x00010000, // Address Length
)
})
}
}
Also the following found in linux's /var/log/messages:
"acpi INTC1026:00: GPIO: looking up 0 in _CRS", indicating the PMC
ACPI device was found and its _CRS was locatable.
Change-Id: I665c873d8a80bd503acc4a9f0241c7a6ea425e16
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Current implementation returns the incorrect GPIO community PID.
The GPIO community index 3 should return PID for COMM_4 and index
4 should return PID for COMM_5.
TEST=Verify PCR port id is correct for each community.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5dc48e5b31f43853b3a613c17f13f7df71f1fbfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41725
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CPU to PCH method refers to PCH ACPI operation region which was wrongly
defined as SystemMemory and PCH_PWRM_BASE_ADDRESS. Change the operation
region to be SystemIO and ACPI_BASE_ADDRESS.
BUG=b:156530805
TEST=Built and booted to kernel.
Signed-off-by: John zhao <john.zhao@intel.com>
Change-Id: Ifa291a993ec23e1e4dfad8f6cdfabc80b824d20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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CPU to PCH method refers to PCH ACPI operation region which was wrongly
defined as SystemIO. This causes ACPI AE_LIMIT error from PM _DSW
method. Change the operation region from SystemIO to SystemMemory to
resolve this execution failure.
BUG=b:140290596
TEST=Built and booted to kernel. _DSW method executes successfully without
ACPI AE_LIMIT error.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I3965c3d891f7d3cf4a448edc0c3f7e7749a905a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Current Interrupt setting use 2nd parameters as device function number.
- Correct as interrupt pin number according to _PRT package format.
{Address, pin, Source, Source index}
- Use irq number directly rather than irq definition as its number
is not for PCI device.
The issue found while enabling GBE and GBE interrupt is not working
without this change.
Reference
- ACPI spec 6.2.13 _PRT
- FSP reference code:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c
- BIOS reference code:
https://github.com/otcshare/CCG-TGL-Generic-Full/blob/master/
TigerLakeBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl
TEST=boot to OS with GBE enabled and check GBE interrupt
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8084b30c668c155ebabbee90b5f70054813b328e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41153
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This replaces GPLv2-or-later and GPLv2-only long form text with the
short SPDX identifiers.
Commands used:
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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That makes it easier to identify "license only" headers (because they
are now license only)
Script line used for that:
perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist...
Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Kernel pinctrl driver changed for Tiger Lake and went to old scheme.
Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/
third_party/kernel/+/2116670
BUG=b:151683980
BRANCH=none
TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl
verify INTC34C5:00 listing all the pins.
Cq-Depend:chromium:2116670
Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39801
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PMC supports messages that can be used for configuring the USB
Type-C Multiplexer/Demultiplexer.
BUG=b:151646486
TEST=Booted to kernel on volteer board and verified PMC and Mux
agent devices identification.
Change-Id: I00c5f929b2eea5de3f8eba794dbe9b36c8083c52
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Update interrupt setting based on latest FSP(3163.01)
Reference:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c
BUG=b:155315876
BRANCH=none
TEST=Build with new FSP(3163.01) and boot OS and login OS console
in ripto/volteer. Without this change, we can't login due to mismatch
interrupt setting between asl and fsp setting.
Cq-Depend: chrome-internal:2944102
Cq-Depend: chrome-internal:2939733
Cq-Depend: chrome-internal:2943140
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40872
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds GPID, a helper method to look up GPIO community ID for
an index.
This patch also includes Intel's common GPIO ASL code. CGPM method in
the common code uses the GPID method introduced in this patch.
BUG=b:148892882
BRANCH=none
TEST="BUILD volteer and ripto"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Id6a00fb8adef0285d6bbc35cd5a44539bd3be6b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40478
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Type-C subsystem power management support for RTD3.
BUG=b:140290596
TEST=Include "tcss.asl" in platform "dsdt.asl" for coreboot build
with the firmware CM. Added acpi debug and booted to kernel. Probed
devices PM_STATE transition from D0 to D3 entry/exit while system at S0.
TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3, offset:0xA4, PM_STATE:D3HT.
xhci:00:0d.0, offset:0x74, PM_STATE:D0D3.
dma:00:0d.2/00.0d.3, offset:0x84, PM_STATE:PMST.
Verified xhci/dma/pcie root ports power runtime_status to be suspended and suspended
time tick through /sys/bus/pci/devices/bus:device:func/power.
Change-Id: I127d3700ad426a44639ee93b4477be6638b42e1b
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Remove EMMC and SD card ACPI devices copied from Ice Lake.
Tiger Lake does not support these controllers.
BUG=b:151208782
TEST= Build volteer board
Change-Id: I4b3e37f93b94757d16d775fb27bee644d9dc539e
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40228
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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HSA -> HDA (High Definition Audio)
Change-Id: Ic0e6ad7b26105fdd6eca6cd11edcf2236e5c7123
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I482715c166ccf5d2f3cc25118d25b07dbfd6650a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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This implementation removes all JSL references from the TGL SoC code.
Additionally, mainboard code changes are done to support build.
BUG=b:150217037
TEST=build tglrvp and volteer
Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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PMC core driver in OS provides debug hooks to developers and end users
to quickly figure out why their platform is not entering a deeper idle
state such as S0ix. This patch adds INT33A1, a required ACPI device,
to support that PMC core driver in tigerlake platform.
BUG=b:146236297
BRANCH=none
TEST="Build and flash volteer and verify it boots to kernel.
Checked for valid files under /sys/kernel/debug/pmc_core."
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ib7e583dc2943461a41d2a7ebde1f16a58a118975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39587
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Method RAOW is assuming that the first argument is a Field object
and writing to it expecting the register to get updated. However,
the callers are passing in the value of the Field object instead.
This eventually is resulting the IMGCLK not getting enable/disabled on the
platform.
Fix this by sending the exact address of the register to be updated.
Also MCCT was setting the clock frequency in both case i.e, Clock Enable
and Disable. Split the MCCT method in two, MCON and MCOF to fix the sequencing
like below
MCON:
Set frequency
Enable clock
MCOF:
Disable clock
Also, make use of MCON and MCOF methods for camera clock control in tglrvp.
This is to avoid the buildbot marking the patch unstable.
BUG=None
BRANCH=None
TEST=Build and Boot waddledoo board and verified that IMGCLKOUT for
world facing camera is enabled/disabled and able to capture images.
Build and Boot Tiger Lake RVP board and verified that IMGCLKOUT for
world facing camera is enabled/disabled and able to capture images.
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I8b886255d5f38819502ae1f4af0851b5a0922b22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39498
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ACPI Object for ISH SSDT
Enable/disable ISH based on devicetree
BRANCH=none
BUG=b:145946347
TEST=boot to OS with TGL RVP UP3
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Change PMC IPC HID from INT34D2 to INTC1026 along with
new kernel pmc ipc driver.
BUG=b:148949891
BRANCH=none
TEST=Boot on Volteer and validate DP tunneling.
Change-Id: I987e7bf76ad1f8ff534101c80661f7c027a60b51
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Update RP number to 12 according to PCH EDS#576591 vol1 rev1.2.
BUG=b:151208838
TEST=build RVP successfully
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
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Add gpio definition for Jasper Lake gpio controller.
Also created a separate file for JSL and TGL gpio keeping common asl file.
gpio_soc_defs.h must pass correct information/macro values to asl file
for code to work.
GPIO controller includes 4 gpio community and 10 groups. Patch adds
definition for all gpio within community and groups
Updated IRQ mapping for all gpios
TEST=Check if jslrvp and tglrvp code is compiling
Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Tigerlake irq.h and pci_irqs.asl have differences compared to
Jasperlake. Hence renaming irq.h as irq_tgl.h and pci_irqs.asl as
pci_irqs_tgl.asl
Also adding a new file irq_jsl.h and pci_irqs_jsl.asl for Jasperlake
SoC and allowing irq.h and pci_irqs.asl to choose the correct file based
on SoC selected.
BUG=None
BRANCH=None
TEST=Compilation for Jasperlake board is working
Change-Id: Ia8e88f92929fe40d7be1c28947e005cb0d862fcb
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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