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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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Age
Commit message (
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Author
2020-05-11
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-04-06
soc/intel/tigerlake: Use SPDX for GPL-2.0-only files
Angel Pons
2020-04-01
soc/intel/tigerlake: Remove Jasper Lake SoC references
Aamir Bohra
2020-03-18
soc: Remove copyright notices
Patrick Georgi
2020-02-25
soc/intel/common: Update Jasper Lake Device IDs
Meera Ravindranath
2020-02-17
soc/tigerlake: Add Device id for Tiger Lake Dual Core
Srinidhi N Kaushik
2020-02-17
soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774
Wim Vervoorn
2020-02-17
soc/intel{cnl,icl,skl,tgl}/bootblock: Make sure DMI PCR 2770 is set
Wim Vervoorn
2020-02-15
soc/intel/tigerlake: Update PMC Register Base and platform check for JSP
Usha P
2020-01-22
soc/intel/common: Add Elkhartlake Device IDs
Tan, Lean Sheng
2020-01-08
soc/intel/tigerlake: Fix PMC config
Ravi Sarawadi
2019-12-19
soc/intel/tigerlake: Add required header files in pch.c
Aamir Bohra
2019-12-16
soc/intel/tigerlake: Pick correct pmc base reg from pch type
Maulik V Vaghela
2019-12-10
soc/intel/common: Add Jasperlake Device IDs
rkanabar
2019-11-15
soc/intel/{icl,tgl}: Rename pch_early_init() to pch_init()
Subrata Banik
2019-11-14
soc/intel/tigerlake: Include few more Tigerlake device IDs
Subrata Banik
2019-11-09
soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock
Subrata Banik