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path: root/src/soc/intel/tigerlake/chip.h
AgeCommit message (Expand)Author
2020-03-30soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3Brandon Breitenstein
2020-03-25soc/intel/tigerlake: Configure HyperthreadingWonkyu Kim
2020-03-18soc: Remove copyright noticesPatrick Georgi
2020-03-15soc/intel/tigerlake: Enable CNVi through dev_enabledSrinidhi N Kaushik
2020-03-15soc/intel/tigerlake: Update Cpu Ratio settingsSrinidhi N Kaushik
2020-03-12soc/intel/tigerlake: Configure L1Substates for PCH Root portsWonkyu Kim
2020-03-11soc/intel/tigerlake: Correct FSP log interfaceRonak Kanabar
2020-03-10soc/intel/tigerlake: Enable Hybrid storage modeWonkyu Kim
2020-03-06soc/intel/tigerlake: Enable CNVi ModeSrinidhi N Kaushik
2020-03-04src: capitalize 'PCIe'Elyes HAOUAS
2020-03-03soc/intel/tigerlake: Add Jasper lake GPIO supportRonak Kanabar
2020-03-01soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by KconfigSubrata Banik
2020-02-27soc/intel/tigerlake: Update FSP params for Jasper LakeMaulik V Vaghela
2020-02-17soc/intel/tigerlake: Enable Audio on TGLSrinidhi N Kaushik
2020-02-01soc/intel/tigerlake: Configure TCSS xHCI and xDCIWonkyu Kim
2020-01-28soc/intel/tigerlake: Enable DP ports according to board designWonkyu Kim
2020-01-18soc/intel/tigerlake: Update chip filesRavi Sarawadi
2019-12-12soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.hFurquan Shaikh
2019-11-09soc/intel/tigerlake: Do initial SoC commit till ramstageSubrata Banik