coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-11-02	mb, soc/intel: Reorganize CNVi device entries in devicetree	Furquan Shaikh
2020-10-30	soc/intel/tigerlake: Enable TCSS XHCI device and define port aliases	Duncan Laurie
2020-10-14	soc/intel/tigerlake: Enable and use USB4 PCIe driver	Duncan Laurie
2020-10-13	mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devices	Furquan Shaikh
2020-10-09	soc/intel/tigerlake: Add chipset devicetree	Duncan Laurie