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Some coreboot project code with my work
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intel
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tigerlake
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espi.c
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Author
2021-01-25
soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroring
Michael Niewöhner
2021-01-20
soc/intel/*: drop broken LPC mmio code
Michael Niewöhner
2021-01-08
soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range()
Furquan Shaikh
2020-10-03
soc/intel: Move pch_misc_init() to common code
Subrata Banik
2020-10-03
soc/intel: Move soc_pch_pirq_init() to common code
Subrata Banik
2020-10-03
soc/intel: Move pch_enable_ioapic() to common code
Subrata Banik
2020-07-06
soc/intel: Drop unused `#include <reg_script.h>`
Angel Pons
2020-05-20
soc/intel/tigerlake: Move PMC PCI resources under PMC device
Tim Wawrzynczak
2020-05-11
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-04-06
soc/intel/tigerlake: Use SPDX for GPL-2.0-only files
Angel Pons
2020-04-01
soc/intel/tigerlake: Remove Jasper Lake SoC references
Aamir Bohra
2020-03-18
soc: Remove copyright notices
Patrick Georgi
2020-02-15
soc/intel/tigerlake: Update PMC Register Base and platform check for JSP
Usha P
2019-12-16
soc/intel/tigerlake: Pick correct pmc base reg from pch type
Maulik V Vaghela
2019-11-09
soc/intel/tigerlake: Do initial SoC commit till ramstage
Subrata Banik